1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-26 06:22:56 +02:00
Commit Graph

23 Commits

Author SHA1 Message Date
Anton Korobeynikov
06d645c199 Proper handle loading of effective address of stack slot stuff
llvm-svn: 70737
2009-05-03 13:10:26 +00:00
Anton Korobeynikov
1f9d4dc64d Reverse order of memory arguments
llvm-svn: 70734
2009-05-03 13:09:40 +00:00
Anton Korobeynikov
f3fadcbbda Remove bogus pattern
llvm-svn: 70733
2009-05-03 13:09:24 +00:00
Anton Korobeynikov
cd06be1d13 Add lowering for global address nodes. Not pretty efficient though.
llvm-svn: 70730
2009-05-03 13:08:33 +00:00
Anton Korobeynikov
e02a674ee0 Some early full call lowering draft for direct calls
llvm-svn: 70729
2009-05-03 13:08:13 +00:00
Anton Korobeynikov
b396742d02 Add call frame setup instruction elimination and lowerid for bunch of call-related stuff.
llvm-svn: 70728
2009-05-03 13:07:54 +00:00
Anton Korobeynikov
4fa710b300 Add CALL lowering.
llvm-svn: 70727
2009-05-03 13:07:31 +00:00
Anton Korobeynikov
582d2a335b Add bunch of mem-whatever patterns
llvm-svn: 70726
2009-05-03 13:07:10 +00:00
Anton Korobeynikov
d14ee9eeae Add bunch of reg-mem inst patterns
llvm-svn: 70725
2009-05-03 13:06:46 +00:00
Anton Korobeynikov
7b7a743ea8 Add normal and trunc stores
llvm-svn: 70724
2009-05-03 13:06:26 +00:00
Anton Korobeynikov
91359dcc3b Basic support for mem=>reg moves
llvm-svn: 70723
2009-05-03 13:06:03 +00:00
Anton Korobeynikov
83122b7ef0 Add 8-bit insts. zext behaviour is not modelled yet
llvm-svn: 70722
2009-05-03 13:05:42 +00:00
Anton Korobeynikov
1c0af22261 Add 8-bit regclass and pattern for sext_inreg
llvm-svn: 70721
2009-05-03 13:05:22 +00:00
Anton Korobeynikov
d74b7ab46d Add pattern for OR
llvm-svn: 70720
2009-05-03 13:05:00 +00:00
Anton Korobeynikov
aff90ae4f2 Add reg-imm variants
llvm-svn: 70719
2009-05-03 13:04:41 +00:00
Anton Korobeynikov
ff4332fcde Add hint to nop
llvm-svn: 70718
2009-05-03 13:04:23 +00:00
Anton Korobeynikov
a46b46fa46 Add more instructions
llvm-svn: 70717
2009-05-03 13:04:06 +00:00
Anton Korobeynikov
262c4b9ff9 Add dummy lowering for shifts
llvm-svn: 70715
2009-05-03 13:03:33 +00:00
Anton Korobeynikov
df71fb8a3a We're not going to spend 100% of time in interrupts, do we? :)
llvm-svn: 70713
2009-05-03 13:02:57 +00:00
Anton Korobeynikov
627e169e8e Add simple reg-reg add.
llvm-svn: 70712
2009-05-03 13:02:39 +00:00
Anton Korobeynikov
e9e0353b21 Add code enough for emission of reg-reg and reg-imm moves. This allows us to compile "ret i16 0" properly!
llvm-svn: 70710
2009-05-03 13:02:04 +00:00
Anton Korobeynikov
ebab62b827 Add proper ISD::RET lowering
llvm-svn: 70703
2009-05-03 12:59:50 +00:00
Anton Korobeynikov
d49e584da5 Dummy MSP430 backend
llvm-svn: 70694
2009-05-03 12:57:15 +00:00