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07d8ccec50
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482 Commits

Author SHA1 Message Date
Evan Cheng
07d8ccec50 Instructions with variable operands (variable_ops) can have a number required 
operands. e.g.
def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops),
                "call {*}$dst", [(X86call GR32:$dst)]>;
TableGen should emit operand informations for the "required" operands.

Added a target instruction info flag M_VARIABLE_OPS to indicate the target
instruction may have more operands in addition to the minimum required
operands.

llvm-svn: 28791
 2006-06-15 07:22:16 +00:00
Evan Cheng
3d60e7e72b Allow more use of iPTR in patterns. 
llvm-svn: 28790
 2006-06-15 00:16:37 +00:00
Evan Cheng
434153a2b4 Added support for variable_ops. 
llvm-svn: 28788
 2006-06-14 22:22:20 +00:00
Evan Cheng
191886d10f Fix support for optional input flag. 
llvm-svn: 28784
 2006-06-14 19:27:50 +00:00
Evan Cheng
fe3e6e1967 getOperandNum(): error if specified operand number is out of range. 
llvm-svn: 28775
 2006-06-13 21:47:27 +00:00
Chris Lattner
f506d91be6 Wrap to 80 cols 
llvm-svn: 28743
 2006-06-09 23:59:44 +00:00
Reid Spencer
00ee1dc6ea Don't build tblgen with -pedantic or -Wno-long-long 
llvm-svn: 28638
 2006-06-01 18:20:23 +00:00
Evan Cheng
1e9556ee06 Can't trust NodeDepth when checking for possibility of load folding creating 
a cycle. This increase the search space and will increase compile time (in
practice it appears to be small, e.g. 176.gcc goes from 62 sec to 65 sec)
that will be addressed later.

llvm-svn: 28476
 2006-05-25 20:16:55 +00:00
Evan Cheng
2a4c04d35a Fixed a really ugly bug. The TableGen'd isel is not freeing the "inflight set" 
correctly. That is causing non-deterministic behavior (and possibly preventing
some load folding from happening).

llvm-svn: 28458
 2006-05-25 00:21:44 +00:00
Chris Lattner
b3aa8ccfe0 Don't make zero-sized static arrays 
llvm-svn: 28448
 2006-05-24 17:31:02 +00:00
Chris Lattner
f604017e47 Patches to make the LLVM sources more -pedantic clean. Patch provided 
by Anton Korobeynikov!  This is a step towards closing PR786.

llvm-svn: 28447
 2006-05-24 17:04:05 +00:00
Evan Cheng
accb9d0378 Now that iPTR is a fully resolved type. We end up losing the type check for 
patterns that look like this:

def : Pat<(i32 (X86Wrapper tconstpool  :$dst)), (MOV32ri tconstpool  :$dst)>;

InsertOneTypeCheck should copy the type from the resolved pattern to the
unresolved one as long as there types are different.

llvm-svn: 28389
 2006-05-19 07:24:32 +00:00
Evan Cheng
00c1318055 lib/Target/Target.td 
llvm-svn: 28386
 2006-05-18 20:42:07 +00:00
Evan Cheng
fcdfdcaa96 Don't generate getCalleeSaveReg and getCalleeSaveRegClasses anymore. 
llvm-svn: 28376
 2006-05-18 00:08:46 +00:00
Evan Cheng
3cfed5af84 Typo 
llvm-svn: 28366
 2006-05-17 20:55:51 +00:00
Evan Cheng
5dc3e33623 Remove PointerType from target definition. Use abstract type MVT::iPTR to 
represent pointer type.

llvm-svn: 28363
 2006-05-17 20:37:59 +00:00
Evan Cheng
d4a056116c Allow patterns to refer to physical registers that belong to multiple 
register classes.

llvm-svn: 28323
 2006-05-16 07:05:30 +00:00
Evan Cheng
409dd126bf Noop instruction 
llvm-svn: 28241
 2006-05-12 07:47:00 +00:00
Evan Cheng
3d1e1ffd9b Unused instruction 
llvm-svn: 28240
 2006-05-12 07:42:01 +00:00
Evan Cheng
d6549daf76 Also add super- register classes info. 
llvm-svn: 28221
 2006-05-11 07:30:26 +00:00
Evan Cheng
2af8a9f980 Watch out for the following case: 
1. Use expects a chain output.
2. Node is expanded into multiple target ops.
3. One of the inner node produces a chain, the outer most one doesn't.

llvm-svn: 28209
 2006-05-10 02:47:57 +00:00
Evan Cheng
0655b538d6 Fix a load folding bug. It is exposed by a multi- resulting instructions 
def : Pat<> pattern.

llvm-svn: 28208
 2006-05-10 00:05:46 +00:00
Evan Cheng
87b66b9aec Add sub-register class information. 
llvm-svn: 28195
 2006-05-09 06:34:26 +00:00
Evan Cheng
ca3dc213dc Set isStore of instructions with ISD::TRUNCSTORE root node. 
llvm-svn: 28075
 2006-05-03 02:08:34 +00:00
Chris Lattner
8cbad2f76a Put instruction names into the first non TargetInstrInfo namespace found. 
llvm-svn: 28043
 2006-05-01 23:46:16 +00:00
Chris Lattner
da6162633a instructions can be in different namespaces. Make sure to use the right 
one for each instruction.

llvm-svn: 28038
 2006-05-01 17:01:17 +00:00
Evan Cheng
0bae850dda Formating 
llvm-svn: 28036
 2006-05-01 09:30:17 +00:00
Evan Cheng
efcb0061df Mark instructions whose pattern is (store ...) isStore. 
llvm-svn: 28032
 2006-05-01 09:04:20 +00:00
Evan Cheng
9f21c2daf4 Remove the temporary option: -no-isel-fold-inflight 
llvm-svn: 28012
 2006-04-28 18:54:11 +00:00
Evan Cheng
3466555d87 When isel'ing a node, mark its operands "InFlight" before selecting them. These 
nodes should not be folded into other nodes.
This fixes the miscompilation of PR 749.
Temporarily under flag control.

llvm-svn: 28002
 2006-04-28 02:08:10 +00:00
Nate Begeman
7ed816f900 JumpTable support! What this represents is working asm and jit support for 
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.

llvm-svn: 27947
 2006-04-22 18:53:45 +00:00
Chris Lattner
56e4ca77c6 Don't fill in fields that no longer exist. 
llvm-svn: 27898
 2006-04-20 18:32:22 +00:00
Evan Cheng
adc5e703ca Rename AddedCost to AddedComplexity. 
llvm-svn: 27841
 2006-04-19 20:36:09 +00:00
Evan Cheng
318120f8ad Allow "let AddedCost = n in" to increase pattern complexity. 
llvm-svn: 27834
 2006-04-19 18:07:24 +00:00
Reid Spencer
599a575d0e Add missing things to the distribution. 
llvm-svn: 27650
 2006-04-13 06:27:20 +00:00
Chris Lattner
1659f983ff Fix a typo: Instr* -> Intr* 
llvm-svn: 27568
 2006-04-10 22:02:59 +00:00
Chris Lattner
9f8d5b538e Infer element types for shuffle masks 
llvm-svn: 27456
 2006-04-06 20:36:51 +00:00
Chris Lattner
7f54d730f1 rename a method, to avoid confusion with llvm intrinsics. 
llvm-svn: 27455
 2006-04-06 20:19:52 +00:00
Chris Lattner
9eacf6b01c Adjust the Intrinsics.gen interface a little bit 
llvm-svn: 27345
 2006-04-02 03:35:30 +00:00
Chris Lattner
914742aa1e regenerate 
llvm-svn: 27313
 2006-03-31 21:54:11 +00:00
Chris Lattner
5fabd2c311 Generalize the previous binary operator support and add a string concatenation 
operation.  This implements Regression/TableGen/strconcat.td.

llvm-svn: 27312
 2006-03-31 21:53:49 +00:00
Chris Lattner
ef86937943 Allow bits init values to be used in patterns, turn them into ints. 
llvm-svn: 27286
 2006-03-31 05:25:56 +00:00
Chris Lattner
f9e5ac8c9a Final bugfix for PR724. GCC won't inline varargs functions, so use one to 
validate the prototype of intrinsic functions.  This prevents GCC from going
crazy and inlining too much stuff, eventually running out of memory.

llvm-svn: 27283
 2006-03-31 04:48:26 +00:00
Chris Lattner
7ae6895610 When emitting code for the verifier, instead of emitting each case statement 
independently, batch up checks so that identically typed intrinsics share
verifier code.  This dramatically reduces the size of the verifier function,
which should help avoid GCC running out of memory compiling Verifier.cpp.

llvm-svn: 27281
 2006-03-31 04:24:58 +00:00
Chris Lattner
8fd532e8a4 regenerate 
llvm-svn: 27264
 2006-03-30 22:51:12 +00:00
Chris Lattner
39d2d17cb3 Implement Regression/TableGen/DagDefSubst.ll 
llvm-svn: 27263
 2006-03-30 22:50:40 +00:00
Evan Cheng
86b5b7cf18 Don't sort the names before outputing the intrinsic name table. It causes a 
mismatch against the enum table.
This is a part of Sabre's master plan to drive me nuts with subtle bugs that
happens to only affect x86 be. :-)

llvm-svn: 27237
 2006-03-28 22:25:56 +00:00
Chris Lattner
723cb246c9 Tblgen doesn't like multiple SDNode<> definitions that map to the sameenum value. Split them into separate enums. 
Also, don't emit dynamic checks when we can compute them statically

llvm-svn: 27202
 2006-03-28 00:41:33 +00:00
Chris Lattner
424516c95a Only compute intrinsic valuetypes when in a target .td file. 
llvm-svn: 27197
 2006-03-28 00:15:00 +00:00
Chris Lattner
8a2ffaea1d revert this, it breaks things. 
llvm-svn: 27196
 2006-03-28 00:03:08 +00:00