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Commit Graph

157379 Commits

Author SHA1 Message Date
Diana Picus
8e5e54ba29 [ARM GlobalISel] Bail out for byval
Fallback if we have a byval parameter or argument since we don't support
them yet.

llvm-svn: 319428
2017-11-30 12:23:44 +00:00
Francis Visoiu Mistrih
86edc13433 [CodeGen] Print "%vreg0" as "%0" in both MIR and debug output
As part of the unification of the debug format and the MIR format, avoid
printing "vreg" for virtual registers (which is one of the current MIR
possibilities).

Basically:

* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/%vreg([0-9]+)/%\1/g"
* grep -nr '%vreg' . and fix if needed
* find . \( -name "*.mir" -o -name "*.cpp" -o -name "*.h" -o -name "*.ll" \) -type f -print0 | xargs -0 sed -i '' -E "s/ vreg([0-9]+)/ %\1/g"
* grep -nr 'vreg[0-9]\+' . and fix if needed

Differential Revision: https://reviews.llvm.org/D40420

llvm-svn: 319427
2017-11-30 12:12:19 +00:00
Simon Pilgrim
a48d538e18 [X86][AVX512] Tag binop/rounding/sae instructions scheduler classes
llvm-svn: 319424
2017-11-30 12:01:52 +00:00
Sean Eveson
4b5d214bc5 [MC] Function stack size section.
Summary:
Original RFC: http://lists.llvm.org/pipermail/llvm-dev/2017-August/117028.html

I wasn't sure who to put as reviewers, so please add/remove people as appropriate.

This change adds a '.stack-size' section containing metadata on function stack sizes to output ELF files behind the new -stack-size-section flag. The section contains pairs of function symbol references (8 byte) and stack sizes (unsigned LEB128).

The contents of this section can be used to measure changes to stack sizes between different versions of the compiler or a source base. The advantage of having a section is that we can extract this information when examining binaries that we didn't build, and it allows users and tools easy access to that information just by referencing the binary.

There is a follow up change to add an option to clang.

Thanks.

Reviewers: hfinkel, MatzeB

Reviewed By: MatzeB

Subscribers: thegameg, asb, llvm-commits

Differential Revision: https://reviews.llvm.org/D39788

llvm-svn: 319423
2017-11-30 12:01:16 +00:00
Sam Parker
86faf1fe64 [DAGCombine] Refactor ReduceLoadWidth
visitAND attempts to narrow the width of extending loads that are
then masked off. ReduceLoadWidth already exists for a similar purpose
and handles shifts, so I've moved the code to handle AND nodes there.

Differential Revision: https://reviews.llvm.org/D39595

llvm-svn: 319421
2017-11-30 11:49:11 +00:00
Serge Guelton
ddb7e7b222 Support generic lowering of vector bswap
llvm-svn: 319419
2017-11-30 11:06:22 +00:00
Simon Pilgrim
f231f5c5e5 [X86][AVX512] Tag RCP/RSQRT/GETEXP instructions scheduler classes
llvm-svn: 319418
2017-11-30 10:48:47 +00:00
Jonas Devlieghere
67bae510f8 [dsymutil] Exclude namespace from ifdef in CFBundle
Should fix build failure introduced by r319416 on non-darwin hosts.

llvm-svn: 319417
2017-11-30 10:41:31 +00:00
Jonas Devlieghere
acf1b692f3 [dsymutil] Upstream getBundleInfo implementation
This patch implements `getBundleInfo`, which uses CoreFoundation to
obtain information about the CFBundle. This information is needed to
populate the Plist in the dSYM bundle.

This change only applies to darwin and is an NFC as far as other
platforms are concerned.

Differential revision: https://reviews.llvm.org/D40244

llvm-svn: 319416
2017-11-30 10:25:28 +00:00
Hiroshi Inoue
24a4e6aa45 Revert rL319407: [SROA] enable splitting for non-whole-alloca loads and stores
This reverts commit rL319407 due to failures in some buildbot.

llvm-svn: 319410
2017-11-30 08:29:51 +00:00
Jonas Paulsson
86695846b9 [SystemZ] Bugfix in adjustSubwordCmp.
Csmith generated a program where a store after load to the same address did
not get chained after the new load created during DAG legalizing, and so
performed an illegal overwrite of the expected value.

When the new zero-extending load is created, the chain users of the original
load must be updated, which was not done previously.

A similar case was also found and handled in lowerBITCAST.

Review: Ulrich Weigand
https://reviews.llvm.org/D40542

llvm-svn: 319409
2017-11-30 08:18:50 +00:00
Hiroshi Inoue
95d5529edc [SROA] enable splitting for non-whole-alloca loads and stores
Currently, SROA splits loads and stores only when they are accessing the whole alloca.
This patch relaxes this limitation to allow splitting a load/store if all other loads and stores to the alloca are disjoint to or fully included in the current load/store. If there is no other load or store that crosses the boundary of the current load/store, the current splitting implementation works as is.
The whole-alloca loads and stores meet this new condition and so they are still splittable.

Here is a simplified motivating example.

struct record {
    long long a;
    int b;
    int c;
};

int func(struct record r) {
    for (int i = 0; i < r.c; i++)
        r.b++;
    return r.b;
}

When updating r.b (or r.c as well), LLVM generates redundant instructions on some platforms (such as x86_64, ppc64); here, r.b and r.c are packed into one 64-bit GPR when the struct is passed as a method argument.

With this patch, the above example is compiled into only few instructions without loop.
Without the patch, unnecessary loop-carried dependency is introduced by SROA and the loop cannot be eliminated by the later optimizers.

Differential Revision: https://reviews.llvm.org/D32998

llvm-svn: 319407
2017-11-30 07:44:46 +00:00
Craig Topper
7693ccf915 [X86] Optimize avx2 vgatherqps for v2f32 with v2i64 index type.
Normal type legalization will widen everything. This requires forcing 0s into the mask register. We can instead choose the form that only reads 2 elements without zeroing the mask.

llvm-svn: 319406
2017-11-30 07:01:40 +00:00
Craig Topper
a9ba95e8f2 [X86] Make sure we don't remove sign extends of masks with AVX2 masked gathers.
We don't use k-registers and instead use the MSB so we need to make sure we sign extend the mask to the msb.

llvm-svn: 319405
2017-11-30 06:31:31 +00:00
Dean Michael Berris
51595f2d85 [XRay][docs] Update documentation on new default for xray_naive_log=
We've recently changed the default for `xray_naive_log=` to be `false`
instead of `true` to make it more consistent with the FDR mode logging
implementation. This means we will now ask users to explicitly choose
which version of the XRay logging is being used.

llvm-svn: 319400
2017-11-30 05:35:51 +00:00
Graham Yiu
8a2253aa71 - Removed unused lamba (IsReturnBlock) causing build bots to fail for r319398
- Added lit testcases that were supposed to be part of r319398

llvm-svn: 319399
2017-11-30 03:36:57 +00:00
Graham Yiu
f7b362a6e8 With PGO information, we can do more aggressive outlining of cold regions in the inline candidate function. This contrasts with the scheme of keeping only the 'early return' portion of the inline candidate and outlining the rest of the function as a single function call.
Support for outlining multiple regions of each function is added, as well as some basic heuristics to determine which regions are good to outline. Outline candidates limited to regions that are single-entry & single-exit. We also avoid outlining regions that produce live-exit variables, which may inhibit some forms of code motion (like commoning).

Fallback to the regular partial inlining scheme is retained when either i) no regions are identified for outlining in the function, or ii) the outlined function could not be inlined in any of its callers.

Differential Revision: https://reviews.llvm.org/D38190

llvm-svn: 319398
2017-11-30 02:41:36 +00:00
Kostya Serebryany
6fc7ac89bc [libFuzzer] mention one more trophie in the Linux Kernel
llvm-svn: 319397
2017-11-30 02:26:47 +00:00
Matt Arsenault
c83ca64857 AMDGPU: Allow negative MUBUF vaddr for gfx9
GFX9 does not enable bounds checking for the resource descriptors
used for private access, so it should be OK to use vaddr with
a potentially negative value.

llvm-svn: 319393
2017-11-30 00:52:40 +00:00
Rafael Espindola
28dc39af8c Check alignment in getSectionContentsAsArray.
While the ArrayRef can technically have unaligned data, it would be
extremely surprising if iterating over it caused undefined behavior
when a reference to the underlying type was bound.

llvm-svn: 319392
2017-11-30 00:44:22 +00:00
Vedant Kumar
4aceb25b2c [Coverage] Use the most-recent completed region count (PR35437)
This is a fix for the coverage segment builder.

If multiple regions must be popped off the active stack at once, and
more than one of them end at the same location, emit a segment using the
count from the most-recent completed region.

Fixes PR35437, rdar://35760630

Testing: invoked llvm-cov on a stage2 build of clang, additional unit
tests, check-profile

llvm-svn: 319391
2017-11-30 00:28:23 +00:00
Peter Collingbourne
82d9236fa4 LowerTypeTests: Deduplicate code. NFC.
llvm-svn: 319390
2017-11-30 00:27:08 +00:00
Peter Collingbourne
2183142a40 LowerTypeTests: Remove unnecessary cast. NFC.
llvm-svn: 319387
2017-11-30 00:02:55 +00:00
Craig Topper
d52b310ee4 [X86] Remove some questionable looking code that seems to be looking through a VZEXT to create a larger VSEXT.
If the input the vzext was signed this would do the wrong thing.

Not sure how to test this.

llvm-svn: 319382
2017-11-29 23:08:25 +00:00
Joerg Sonnenberger
bce7c549c3 First step towards more human-friendly PPC assembler output:
- add -ppc-reg-with-percent-prefix option to use %r3 etc as register
  names
- split off logic for Darwinish verbose conditional codes into a helper
  function
- be explicit about Darwin vs AIX vs GNUish assembler flavors

Based on the patch from Alexandre Yukio Yamashita

Differential Revision: https://reviews.llvm.org/D39016

llvm-svn: 319381
2017-11-29 23:05:56 +00:00
Sam Clegg
4ab3c5e5a7 [WebAssembly] Update test expectations for gcc torture tests
I believe these were recently fixed by:
https://reviews.llvm.org/rL319186

Differential Revision: https://reviews.llvm.org/D40619

llvm-svn: 319380
2017-11-29 23:05:50 +00:00
Zachary Turner
6d6f79e129 [CodeView] Factor some code out of TypeTableBuilder.
This class had some code that would automatically remap type
indices before hashing and serializing.  The only caller of
this method was the TypeStreamMerger anyway, and the method
doesn't make general sense, and prevents making certain future
improvements to the class.  So, factoring this up one level
into the TypeStreamMerger where it belongs.

llvm-svn: 319377
2017-11-29 22:41:56 +00:00
Craig Topper
b027bfa2db [SelectionDAG][X86] Teach promotion legalization for fp_to_sint/fp_to_uint to insert an assertsext/assertzext based on the original type
If we put in an assertsext/zext here, we're able to generate better truncate code using pack on pre-avx512 targets.

Similar is already done during type legalization. This is the equivalent for op legalization

Differential Revision: https://reviews.llvm.org/D40591

llvm-svn: 319368
2017-11-29 22:15:43 +00:00
Dan Gohman
881766b860 [WebAssembly] Fix fptoui lowering bounds
To fully avoid trapping on wasm, fptoui needs a second check to ensure that
the operand isn't below the supported range.

llvm-svn: 319354
2017-11-29 20:20:11 +00:00
Sam Clegg
d69529fdff Add libstd++-4.8 exceptions to ubsan_blacklist.txt
Differential Revision: https://reviews.llvm.org/D40589

llvm-svn: 319353
2017-11-29 20:10:14 +00:00
Krzysztof Parzyszek
ac90d004e1 [Hexagon] Remove HexagonISD::PACKHL
llvm-svn: 319352
2017-11-29 19:59:29 +00:00
Krzysztof Parzyszek
7ef10d3f2b [Hexagon] Create helpers extractVector and insertVector in lowering
llvm-svn: 319351
2017-11-29 19:58:10 +00:00
Simon Pilgrim
e19432f57e [X86][AVX512] Tag RCP/RSQRT/GETEXP instructions scheduler classes (REVERSION)
Accidental commit of incomplete patch

llvm-svn: 319346
2017-11-29 19:37:38 +00:00
Zachary Turner
1e7c2158fe Make TypeTableBuilder inherit from TypeCollection.
A couple of places in LLD were passing references to
TypeTableCollections around, which makes it hard to change the
implementation at runtime.  However, these cases only needed to
iterate over the types in the collection, and TypeCollection
already provides a handy abstract interface for this purpose.

By implementing this interface, we can get rid of the need to
pass TypeTableBuilder references around, which should allow us
to swap the implementation at runtime in subsequent patches.

llvm-svn: 319345
2017-11-29 19:35:21 +00:00
Zachary Turner
f34723dcab Fix line endings in llvm-pdbutil.cpp
llvm-svn: 319340
2017-11-29 19:29:25 +00:00
Simon Pilgrim
6c0c41d948 [X86][AVX512] Tag RCP/RSQRT/GETEXP instructions scheduler classes
llvm-svn: 319338
2017-11-29 19:19:59 +00:00
Simon Pilgrim
5443a8a118 [X86][AVX512] Tag 3OP (shuffles, double-shifts and GFNI) instructions scheduler classes
llvm-svn: 319337
2017-11-29 18:52:20 +00:00
Nirav Dave
201c2b02d5 [ARM][DAG] Revert Disable post-legalization store merge for ARM
Partially reverting enabling of post-legalization store merge
(r319036) for just ARM backend as it is causing incorrect code
in some Thumb2 cases.

llvm-svn: 319331
2017-11-29 18:06:13 +00:00
Greg Bedwell
5c717562d9 [cmake] Replace -Wall with /W4 in clang-cl options now that -Wall aliases -Weverything
Instead, reuse the code-path for cl.exe that adds /W4 , which for clang-cl
aliases clang's "-Wall -Wextra" which matches what clang-cl's /Wall
previously aliased.

This should restore the verbosity of a Windows selfhost build back to
its previous levels.

Differential Revision: https://reviews.llvm.org/D40603

llvm-svn: 319330
2017-11-29 18:05:32 +00:00
Greg Bedwell
be0f0e6e2f Make check-lit tests respect LLVM_LIT_TOOLS_DIR
Differential Revision: https://reviews.llvm.org/D40520

llvm-svn: 319329
2017-11-29 18:05:26 +00:00
Zaara Syeda
4c63aa3c75 [Power9] add more tests for D38287; NFC
llvm-svn: 319328
2017-11-29 17:26:20 +00:00
Sanjay Patel
8237547da0 [InstCombine] add tests for select-of-constants; NFC
These are variants of a test that was originally added in:
https://reviews.llvm.org/rL75531
...but removed with:
https://reviews.llvm.org/rL159230

llvm-svn: 319327
2017-11-29 17:21:39 +00:00
Simon Pilgrim
fbd6e404f1 [X86][AVX512] Add itinerary argument to all AVX512_maskable_* wrappers. NFCI
All default to NoItinerary

llvm-svn: 319326
2017-11-29 17:21:15 +00:00
Adam Nemet
2885645683 Add opt-viewer testing
Detects whether we have the Python modules (pygments, yaml) required by
opt-viewer and hooks this up to REQUIRES.

This fixes https://bugs.llvm.org/show_bug.cgi?id=34129 (the lack of opt-viewer
testing).

It's also related to https://github.com/apple/swift/pull/12938 and the idea is
to expose LLVM_HAVE_OPT_VIEWER_MODULES to the Swift cmake.

Differential Revision: https://reviews.llvm.org/D40202

Fixes since the first commit:
1. Disable syntax highlighting as different versions of pygments generate
different HTML
2. Use llvm-cxxfilt from the build

llvm-svn: 319324
2017-11-29 17:07:41 +00:00
Sander de Smalen
f54f612a70 Reverted r319315 because of unused functions (due to PPR not yet being
used by any instructions).

llvm-svn: 319321
2017-11-29 15:14:39 +00:00
Simon Pilgrim
97088da9e8 [X86][AVX512] Tag VPERMILV instruction scheduler class
llvm-svn: 319316
2017-11-29 14:58:34 +00:00
Sander de Smalen
a1e07e5345 [AArch64][SVE] Asm: Add SVE predicate register definitions and parsing support
Summary: Patch [1/4] in a series to add parsing of predicates and properly parse SVE ZIP1/ZIP2 instructions.

Reviewers: rengolin, kristof.beyls, fhahn, mcrosier, evandro, echristo, efriedma

Reviewed By: fhahn

Subscribers: aemerson, javed.absar, llvm-commits, tschuett

Differential Revision: https://reviews.llvm.org/D40360

llvm-svn: 319315
2017-11-29 14:34:18 +00:00
Diana Picus
ded22a182d [ARM GlobalISel] Fix selecting G_BRCOND
When lowering a G_BRCOND, we generate a TSTri of the condition against
1, which sets the flags, and then a Bcc which branches based on the
value of the flags.

Unfortunately, we were using the wrong condition code to check whether
we need to branch (EQ instead of NE), which caused all our branches to
do the opposite of what they were intended to do. This patch fixes the
issue by using the correct condition code.

llvm-svn: 319313
2017-11-29 14:20:06 +00:00
Simon Pilgrim
3df6922e61 [X86][AVX512] Setup unary (PABS/VPLZCNT/VPOPCNT/VPCONFLICT/VMOV*DUP) instruction scheduler classes
llvm-svn: 319312
2017-11-29 13:49:51 +00:00
Dmitry Preobrazhensky
d68c59f82f [AMDGPU][MC][GFX9] Corrected mapping of GFX9 v_add/sub/subrev_u32
When translating pseudo to MC, v_add/sub/subrev_u32 shall be mapped via a separate table as GFX8 has opcodes with the same names.
These instructions shall also be labelled as renamed for pseudoToMCOpcode to handle them correctly.

Reviewers: arsenm

Differential Revision: https://reviews.llvm.org/D40550

llvm-svn: 319311
2017-11-29 13:33:40 +00:00