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0966883093
Commit Graph

31 Commits

Author SHA1 Message Date
Evan Cheng
0966883093 Fix VFP conversion instruction encodings. 
llvm-svn: 59104
 2008-11-12 06:41:41 +00:00
Evan Cheng
39d8bf295d Fix encoding of single-precision VFP registers. 
llvm-svn: 59102
 2008-11-12 02:19:38 +00:00
Evan Cheng
8b7fefc126 Fix FMDRR encoding. 
llvm-svn: 59088
 2008-11-11 22:46:12 +00:00
Evan Cheng
35f1477c5a Encode VFP load / store instructions. 
llvm-svn: 59084
 2008-11-11 21:48:44 +00:00
Evan Cheng
91e4ef91c5 Encode VFP conversion instructions. 
llvm-svn: 59074
 2008-11-11 19:40:26 +00:00
Evan Cheng
3c62bb7471 Encode VFP arithmetic instructions. 
llvm-svn: 59016
 2008-11-11 02:11:05 +00:00
Evan Cheng
aa24d19533 Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 encoding bug. 
llvm-svn: 58800
 2008-11-06 08:47:38 +00:00
Jim Grosbach
a25a322741 udpate header comment: s/VP/VFP/ 
llvm-svn: 56126
 2008-09-11 21:41:29 +00:00
Evan Cheng
11d2c09adc Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF. 
llvm-svn: 48380
 2008-03-15 00:03:38 +00:00
Chris Lattner
6846e346a8 rename SDTRet -> SDTNone. 
Move definition of 'trap' sdnode up from x86 instrinfo to targetselectiondag.td.

llvm-svn: 46017
 2008-01-15 22:02:54 +00:00
Chris Lattner
9b4f2b2316 get def use info more correct. 
llvm-svn: 45821
 2008-01-10 05:12:37 +00:00
Evan Cheng
9de4f35e9f Only mark instructions that load a single value without extension as isSimpleLoad = 1. 
llvm-svn: 45727
 2008-01-07 23:56:57 +00:00
Chris Lattner
14310afe42 rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate. 
llvm-svn: 45667
 2008-01-06 23:38:27 +00:00
Chris Lattner
5489888580 rename isStore -> mayStore to more accurately reflect what it captures. 
llvm-svn: 45656
 2008-01-06 08:36:04 +00:00
Chris Lattner
2bb919b542 remove explicit isStore flags that are now inferrable. 
llvm-svn: 45653
 2008-01-06 05:55:01 +00:00
Chris Lattner
ad9a6ccb83 Remove attribution from file headers, per discussion on llvmdev. 
llvm-svn: 45418
 2007-12-29 20:36:04 +00:00
Evan Cheng
64a1febf9a Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled. 
llvm-svn: 44960
 2007-12-12 23:12:09 +00:00
Evan Cheng
b43255bc68 Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. 
llvm-svn: 41863
 2007-09-11 19:55:27 +00:00
Evan Cheng
8c896cc115 Initial JIT support for ARM by Raul Fernandes Herbster. 
llvm-svn: 40887
 2007-08-07 01:37:15 +00:00
Evan Cheng
8312ed6f77 Change instruction description to split OperandList into OutOperandList and 
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033
 2007-07-19 01:14:50 +00:00
Evan Cheng
abcf3842bb Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit. 
llvm-svn: 38501
 2007-07-10 18:08:01 +00:00
Evan Cheng
d9d3be078c No need for ccop anymore. 
llvm-svn: 37965
 2007-07-06 23:34:09 +00:00
Evan Cheng
ef8a1bcbc3 Each ARM use predicate operand is now made up of two components. The new component is the CPSR register. 
llvm-svn: 37895
 2007-07-05 07:13:32 +00:00
Evan Cheng
7b433a2954 Mark these instructions clobbersPred. They modify the condition code register. 
llvm-svn: 37468
 2007-06-06 10:17:05 +00:00
Evan Cheng
3672d15956 For VFP2 fldm, fstm instructions, the condition code is printed after the address mode and size specifier. e.g. fstmiaseq, not fstmeqias. 
llvm-svn: 37351
 2007-05-29 23:34:19 +00:00
Evan Cheng
9f0ffdf4b3 Add PredicateOperand to all ARM instructions that have the condition field. 
llvm-svn: 37066
 2007-05-15 01:29:07 +00:00
Evan Cheng
73abcaa525 Switch BCC, MOVCCr, etc. to PredicateOperand. 
llvm-svn: 36948
 2007-05-08 21:08:43 +00:00
Evan Cheng
a949d165ee This is no longer needed after enabling the DAG combiner xform. 
llvm-svn: 36909
 2007-05-07 21:29:41 +00:00
Dale Johannesen
d28d0bac2a Evan's patch to avoid FPreg->intreg copy for cvt; store to mem 
llvm-svn: 36693
 2007-05-03 20:54:42 +00:00
Chris Lattner
844e3a4191 match a reassociated form of fnmul. This implements CodeGen/ARM/fnmul.ll 
llvm-svn: 36660
 2007-05-03 00:32:00 +00:00
Evan Cheng
c6e1d453d3 ARM backend contribution from Apple. 
llvm-svn: 33353
 2007-01-19 07:51:42 +00:00