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784 Commits

Author SHA1 Message Date
Craig Topper
0ac9bb8aa1 Merge VPERM2F128/VPERM2I128 ISD node types. 
llvm-svn: 145485
 2011-11-30 07:47:51 +00:00
Craig Topper
43b885cff4 Merge decoding of VPERMILPD and VPERMILPS shuffle masks. Merge X86ISD node type for VPERMILPD/PS. Add instruction selection support for VINSERTI128/VEXTRACTI128. 
llvm-svn: 145483
 2011-11-30 06:25:25 +00:00
Evan Cheng
5c1efd630b Add another missing pattern. llvm-gcc likes f64 but clang likes i64 so it was generating poor code for some SSE builtins. 
llvm-svn: 145448
 2011-11-29 22:48:34 +00:00
Jakob Stoklund Olesen
5d6a4584d9 Make X86::FsFLD0SS / FsFLD0SD real pseudo-instructions. 
Like V_SET0, these instructions are expanded by ExpandPostRA to xorps /
vxorps so they can participate in execution domain swizzling.

This also makes the AVX variants redundant.

llvm-svn: 145440
 2011-11-29 22:27:25 +00:00
Elena Demikhovsky
735cff1fa8 Fixed vsqrt.ss intrinsic usage - order of input operands was wrong. 
Added a test.
Thanks Bruno for reviewing the patch.

llvm-svn: 145403
 2011-11-29 15:00:45 +00:00
Craig Topper
4550fc2649 Fix issues in shuffle decoding around VPERM* instructions. Fix shuffle decoding for VSHUFPS/D for 256-bit types. Add pattern matching for memory forms of VPERMILPS/VPERMILPD. 
llvm-svn: 145390
 2011-11-29 07:49:05 +00:00
Craig Topper
aca91b9f14 Fix VINSERTF128/VEXTRACTF128 to be marked as FP instructions. Allow execution dependency fix pass to convert them to their integer equivalents when AVX2 is enabled. 
llvm-svn: 145376
 2011-11-29 05:37:58 +00:00
Craig Topper
a6c1d25798 Correctly mark VPERM2F128 as being an FP instruction and add execution domain fixing support to convert it to VPERM2I128 for AVX2. 
llvm-svn: 145370
 2011-11-29 03:57:34 +00:00
Evan Cheng
1ed975b097 Add missing avx pattern. 
llvm-svn: 145272
 2011-11-28 20:27:23 +00:00
Craig Topper
6f5a0bc4e3 Add X86 instruction selection for VPERM2I128 when AVX2 is enabled. Merge VPERMILPS/VPERMILPD detection since they are pretty similar. 
llvm-svn: 145238
 2011-11-28 10:14:51 +00:00
Craig Topper
563854a230 Merge 128-bit and 256-bit X86ISD node types for VPERMILPS and VPERMILPD. Simplify some shuffle lowering code since V1 can never be UNDEF due to canonalizing that occurs when shuffle nodes are created. 
llvm-svn: 145153
 2011-11-26 22:55:48 +00:00
Craig Topper
65f8dcdb7d Collapse X86ISD node types for PUNPCKH*, PUNPCKL*, UNPCKLP*, and UNPCKHP* to not be type specific. Now we just have integer high and low and floating point high and low. Pattern matching will choose the correct instruction based on the vector type. 
llvm-svn: 145148
 2011-11-26 20:47:44 +00:00
Craig Topper
e761f42368 Remove 256-bit specific node types for UNPCKHPS/D and instead use the 128-bit versions and let the operand type disinquish. Also fix the load form of the v8i32 patterns for these to realize that the load would be promoted to v4i64. 
llvm-svn: 145126
 2011-11-24 22:57:10 +00:00
Craig Topper
7cf04d32e9 Remove AVX2 specific X86ISD node types for PUNPCKH/L and instead just reuse the 128-bit versions and let the vector type distinguish. 
llvm-svn: 145125
 2011-11-24 22:20:08 +00:00
Craig Topper
866214a486 Lowering for v32i8 to VPUNPCKLBW/VPUNPCKHBW when AVX2 is enabled. 
llvm-svn: 145028
 2011-11-21 08:26:50 +00:00
Craig Topper
14cedf481a Add support for lowering 256-bit shuffles to VPUNPCKL/H for i16, i32, i64 if AVX2 is enabled. 
llvm-svn: 145026
 2011-11-21 06:57:39 +00:00
Craig Topper
e878c775cf Add code for lowering v32i8 shifts by a splat to AVX2 immediate shift instructions. Remove 256-bit splat handling from LowerShift as it was already handled by PerformShiftCombine. 
llvm-svn: 145005
 2011-11-20 00:12:05 +00:00
Craig Topper
6ed413c495 Use 256-bit vcmpeqd for creating an all ones vector when AVX2 is enabled. 
llvm-svn: 145004
 2011-11-19 22:34:59 +00:00
Craig Topper
3e24dc25b2 Remove some of the special classes that worked around an old tablegen limitation of not being able to remove redundant bitconverts from patterns. 
llvm-svn: 145003
 2011-11-19 21:01:54 +00:00
Craig Topper
c6a4cbdc04 Custom lower AVX2 variable shift intrinsics to shl/srl/sra nodes and remove the intrinsic patterns. 
llvm-svn: 144999
 2011-11-19 17:46:46 +00:00
Craig Topper
a64e2604a2 Synthesize SSSE3/AVX 128-bit horizontal integer add/sub instructions from add/sub of appropriate shuffle vectors. 
llvm-svn: 144989
 2011-11-19 09:02:40 +00:00
Craig Topper
117ffc9a0c Collapse X86 PSIGNB/PSIGNW/PSIGND node types. 
llvm-svn: 144988
 2011-11-19 07:33:10 +00:00
Craig Topper
536f9d9434 Extend VPBLENDVB and VPSIGN lowering to work for AVX2. 
llvm-svn: 144987
 2011-11-19 07:07:26 +00:00
Craig Topper
0deee76383 Remove unused parameters from the AVX maskmov classes. 
llvm-svn: 144985
 2011-11-19 04:49:22 +00:00
Nadav Rotem
08f8a75c2c Add AVX2 vpbroadcast support 
llvm-svn: 144967
 2011-11-18 02:49:55 +00:00
Craig Topper
7297509c73 Fix SSE/AVX integer comparison patterns to understand that all integer vector loads are promoted to i64 vector loads so patterns need a bitconvert. Also slightly simplify the AVX2 variable shift patterns by using the predefined bitconvert pattern fragments. 
llvm-svn: 144896
 2011-11-17 07:49:38 +00:00
Craig Topper
4d39196041 Remove seemingly unnecessary duplicate VROUND definitions. 
llvm-svn: 144885
 2011-11-17 07:04:00 +00:00
Evan Cheng
5bae2333cb Another missing X86ISD::MOVLPD pattern. rdar://10450317 
llvm-svn: 144839
 2011-11-16 22:24:44 +00:00
Craig Topper
7a4d482aaa Fix the execution domain on a bunch of SSE/AVX instructions. 
llvm-svn: 144784
 2011-11-16 07:30:46 +00:00
Evan Cheng
2034ff3b0b Add a missing pattern for X86ISD::MOVLPD. rdar://10436044 
llvm-svn: 144566
 2011-11-14 20:35:52 +00:00
Craig Topper
e0b34012db Add neverHasSideEffects, mayLoad, and mayStore to many patternless SSE/AVX instructions. Remove MMX check from LowerVECTOR_SHUFFLE since MMX vector types won't go through it anyway. 
llvm-svn: 144522
 2011-11-14 06:46:21 +00:00
Craig Topper
0458cdf64a Add more AVX2 shift lowering support. Move AVX2 variable shift to use patterns instead of custom lowering code. 
llvm-svn: 144457
 2011-11-12 09:58:49 +00:00
Craig Topper
50df7c3842 Add lowering for AVX2 shift instructions. 
llvm-svn: 144380
 2011-11-11 07:39:23 +00:00
Nadav Rotem
e3d8f1a069 AVX2: Add variable shift from memory. 
Note: These patterns only works in some cases because
many times the load sd node is bitcasted from a load
node of a different type.

llvm-svn: 144266
 2011-11-10 06:54:20 +00:00
Nadav Rotem
ddc6bfa543 AVX2: Add patterns for variable shift operations 
llvm-svn: 144212
 2011-11-09 21:22:13 +00:00
Nadav Rotem
e66a72a2c4 Add AVX2 support for vselect of v32i8 
llvm-svn: 144187
 2011-11-09 13:21:28 +00:00
Craig Topper
7ff77dc2b1 Add instruction selection for AVX2 integer comparisons. 
llvm-svn: 144176
 2011-11-09 08:06:13 +00:00
Evan Cheng
4a63100fe3 Add x86 isel logic and patterns to match movlps from clang generated IR for _mm_loadl_pi(). rdar://10134392, rdar://10050222 
llvm-svn: 144052
 2011-11-08 00:31:58 +00:00
Craig Topper
7eab73f510 Add AVX2 variable shift instructions and intrinsics. 
llvm-svn: 143915
 2011-11-07 08:26:24 +00:00
Craig Topper
b1ef950217 Add AVX2 VPMOVMASK instructions and intrinsics. 
llvm-svn: 143904
 2011-11-07 03:20:35 +00:00
Craig Topper
d422190c0f Add AVX2 VEXTRACTI128 and VINSERTI128 instructions. Fix VPERM2I128 to be qualified with HasAVX2 instead of HasAVX. Mark VINSERTF128 and VEXTRACTF128 as never having side effects. 
llvm-svn: 143902
 2011-11-07 02:00:04 +00:00
Craig Topper
01b852b95a More AVX2 instructions and their intrinsics. 
llvm-svn: 143895
 2011-11-06 23:04:08 +00:00
Craig Topper
31b1d79474 Add more AVX2 instructions and intrinsics. 
llvm-svn: 143861
 2011-11-06 06:12:20 +00:00
Craig Topper
80cdc1ee12 Add intrinsics for X86 vcvtps2ph and vcvtph2ps instructions 
llvm-svn: 143683
 2011-11-04 06:59:49 +00:00
Craig Topper
124b2fd08c Add new X86 AVX2 VBROADCAST instructions. 
llvm-svn: 143612
 2011-11-03 07:35:53 +00:00
Craig Topper
a2a55bd0b4 More AVX2 instructions and intrinsics. 
llvm-svn: 143536
 2011-11-02 06:54:17 +00:00
Craig Topper
c5482eb697 Add a bunch more X86 AVX2 instructions and their corresponding intrinsics. 
llvm-svn: 143529
 2011-11-02 04:42:13 +00:00
Craig Topper
6eaf58df7c Begin adding AVX2 instructions. No selection support yet other than intrinsics. 
llvm-svn: 143331
 2011-10-31 02:15:10 +00:00
Jakob Stoklund Olesen
d7827f928d V_SET0 has no side effects. 
TableGen will mark any pattern-less instruction as having unmodeled side
effects. This is extra bad for V_SET0 which gets rematerialized a lot.

This was part of the cause for PR11125, but the real bug was fixed
in r141923.

llvm-svn: 141924
 2011-10-14 00:39:50 +00:00
Craig Topper
0d25fa802f Add 'implicit EFLAGS' to patterns for popcnt and lzcnt 
llvm-svn: 141853
 2011-10-13 06:18:52 +00:00