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Commit Graph

3170 Commits

Author SHA1 Message Date
Rui Ueyama
0acac7750e Object/COFF: change data type of SymbolNumber from int16 to uint16.
Microsoft PE/COFF Spec clearly states that the field is of signed interger
type. However, in reality, it's unsigned. If cl.exe needs to create a large
number of sections for COMDAT sections, it will just create more than 32768
sections. Handling large section number as negative number is not correct.
I think this is a spec bug.

Differential Revision: http://llvm-reviews.chandlerc.com/D3088

llvm-svn: 203986
2014-03-15 00:04:08 +00:00
Rafael Espindola
cbee162fdf Correctly handle an ELF symbol defined with "a = b + expr".
We were marking the symbol as absolute instead of computing b's offset + the
expression value.

This fixes pr19126.

llvm-svn: 203962
2014-03-14 20:09:04 +00:00
Oliver Stannard
f2a05b4899 Generalise assembly tests to not rely on anonymous symbol names
llvm-svn: 203909
2014-03-14 09:10:26 +00:00
Rafael Espindola
28e86f1f9b Use printable names to implement directional labels.
This changes the implementation of local directional labels to use a dedicated
map. With that it can then just use CreateTempSymbol, which is what the rest
of MC uses.

CreateTempSymbol doesn't do a great job at making sure the names are unique
(or being efficient when the names are not needed), but that should probably
be fixed in a followup patch.

This fixes pr18928.

llvm-svn: 203826
2014-03-13 18:09:26 +00:00
Elena Demikhovsky
d3e6f6628c AVX-512: masked load/store + intrinsics for them.
llvm-svn: 203790
2014-03-13 12:05:52 +00:00
Hal Finkel
8b6358ead9 [PowerPC] Initial support for the VSX instruction set
VSX is an ISA extension supported on the POWER7 and later cores that enhances
floating-point vector and scalar capabilities. Among other things, this adds
<2 x double> support and generally helps to reduce register pressure.

The interesting part of this ISA feature is the register configuration: there
are 64 new 128-bit vector registers, the 32 of which are super-registers of the
existing 32 scalar floating-point registers, and the second 32 of which overlap
with the 32 Altivec vector registers. This makes things like vector insertion
and extraction tricky: this can be free but only if we force a restriction to
the right register subclass when needed. A new "minipass" PPCVSXCopy takes care
of this (although it could do a more-optimal job of it; see the comment about
unnecessary copies below).

Please note that, currently, VSX is not enabled by default when targeting
anything because it is not yet ready for that.  The assembler and disassembler
are fully implemented and tested. However:

 - CodeGen support causes miscompiles; test-suite runtime failures:
      MultiSource/Benchmarks/FreeBench/distray/distray
      MultiSource/Benchmarks/McCat/08-main/main
      MultiSource/Benchmarks/Olden/voronoi/voronoi
      MultiSource/Benchmarks/mafft/pairlocalalign
      MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4
      SingleSource/Benchmarks/CoyoteBench/almabench
      SingleSource/Benchmarks/Misc/matmul_f64_4x4

 - The lowering currently falls back to using Altivec instructions far more
   than it should. Worse, there are some things that are scalarized through the
   stack that shouldn't be.

 - A lot of unnecessary copies make it past the optimizers, and this needs to
   be fixed.

 - Many more regression tests are needed.

Normally, I'd fix these things prior to committing, but there are some
students and other contributors who would like to work this, and so it makes
sense to move this development process upstream where it can be subject to the
regular code-review procedures.

llvm-svn: 203768
2014-03-13 07:58:58 +00:00
Saleem Abdulrasool
8a5cd123df ARM: support emission of complex SO expressions
Support to the IAS was added to actually parse and handle the complex SO
expressions.  However, the object file lowering was not updated to compensate
for the fact that the shift operand may be an absolute expression.

When trying to assemble to an object file, the lowering would fail while
succeeding when emitting purely assembly.  Add an appropriate test.

The test case is inspired by the test case provided by Jiangning Liu who also
brought the issue to light.

llvm-svn: 203762
2014-03-13 07:02:41 +00:00
Roman Divacky
023131bd23 Allow exclamation and tilde to be parsed as a part of the ppc asm operand.
llvm-svn: 203699
2014-03-12 19:25:57 +00:00
Rafael Espindola
9eaa756fe4 Try harder to evaluate expressions when printing assembly.
When printing assembly we don't have a Layout object, but we can still
try to fold some constants.

Testcase by Ulrich Weigand.

llvm-svn: 203677
2014-03-12 16:55:59 +00:00
Sasa Stankovic
018056201a [mips] Implement NaCl sandboxing of function calls:
* Add masking instructions before indirect calls (in MC layer).
  * Align call + branch delay to the bundle end (in MC layer).

Differential Revision: http://llvm-reviews.chandlerc.com/D3032

llvm-svn: 203606
2014-03-11 21:23:40 +00:00
Sasa Stankovic
37538d4bfa [mips] Implement NaCl sandboxing of loads, stores and SP changes:
* Add masking instructions before loads and stores (in MC layer).
  * Add masking instructions after SP changes (in MC layer).
  * Forbid loads, stores and SP changes in delay slots (in MI layer).

Differential Revision: http://llvm-reviews.chandlerc.com/D2904

llvm-svn: 203484
2014-03-10 20:34:23 +00:00
Matheus Almeida
4fff721d3a [mips] Assembly parser must invoke the target streamer to handle .set reorder macro.
llvm-svn: 203459
2014-03-10 13:21:10 +00:00
Venkatraman Govindaraju
a11c82efc1 [Sparc] Add support for decoding 'swap' instruction.
llvm-svn: 203424
2014-03-09 23:32:07 +00:00
Sasa Stankovic
5f4d984f32 Moved test file from test/MC/Mips to test/CodeGen/Mips.
llvm-svn: 203298
2014-03-07 22:08:46 +00:00
Duncan P. N. Exon Smith
a9db25cef0 ARM: Make .unreq directives case-insensitive
Be case-insensitive when processing .unreq directives.

Patch by Lin Zuojian!

llvm-svn: 203251
2014-03-07 16:16:52 +00:00
Elena Demikhovsky
71d04d27da AVX-512: Added rrk, rrkz, rmk, rmkz, rmbk, rmbkz versions of AVX512 FP packed instructions, added encoding tests for them.
By Robert Khazanov.

llvm-svn: 203098
2014-03-06 08:45:30 +00:00
Elena Demikhovsky
2b2f00d0f2 AVX-512: fixed comressed displacement - by Robert Khazanov
llvm-svn: 203096
2014-03-06 08:15:35 +00:00
Vladimir Medic
5c28631a7b This patch implements .set dsp directive and sets appropriate feature bits.This directive is a counterpart of -mattr=dsp command line option with the exception that it does not influence elf header flags. The usage example is gives in test file.
llvm-svn: 202966
2014-03-05 11:05:09 +00:00
Vladimir Medic
8272ae6789 This patch implements .set mips32r2 directive and sets appropriate feature bits. It also introduces helper functions that are used to set and clear feature bits as necessary. This directive is a counterpart of -mips32r2 command line options with the exception that it does not influence elf header flags. The usage example is gives in test file.
llvm-svn: 202807
2014-03-04 09:54:09 +00:00
Kevin Qin
8d741b5791 [AArch64]Fix improper diagnostics about offset range of load/store instructions.
llvm-svn: 202775
2014-03-04 02:05:13 +00:00
Reid Kleckner
ec58432880 MC: Fix Intel assembly parser for [global + offset]
We were dropping the displacement on the floor if we also had some
immediate offset.

Should fix PR19033.

llvm-svn: 202774
2014-03-04 00:33:17 +00:00
Ed Maste
1644c2608f [mips] support FK_Data_2 and FK_Data_8 to fix big-endian debug data
This fixes invalid lengths in .debug_aranges on big-endian mips64
(lengths appear to be left-shifted by 32 bits) and in .debug_loc.

Differential Revision: http://llvm-reviews.chandlerc.com/D2517

llvm-svn: 202716
2014-03-03 14:27:49 +00:00
Vladimir Medic
c17b0032b0 This patch implements jalx instruction for Mips architecture.This instruction executes a procedure call within the current 256 MB-aligned region and change the ISA Mode from MIPS32 to microMIPS32 or MIPS16e. Usage samples for assembler and dissasembler are provided as well.
llvm-svn: 202706
2014-03-03 13:12:59 +00:00
Saleem Abdulrasool
ceb96bcf7f AsmParser: add missed tests
The diagnostics tests were missing from the previous introduction of ifeqs.

llvm-svn: 202674
2014-03-03 06:35:00 +00:00
Venkatraman Govindaraju
34b3409b1a [Sparc] Add trap on integer condition codes (Ticc) instructions to Sparc backend.
llvm-svn: 202670
2014-03-02 23:39:07 +00:00
Venkatraman Govindaraju
773ff0c22b [Sparc] Add return/rett instruction to Sparc backend.
llvm-svn: 202666
2014-03-02 22:55:53 +00:00
Venkatraman Govindaraju
b64b412386 [Sparc] Add support for decoding jmpl/retl/ret instruction.
llvm-svn: 202663
2014-03-02 21:17:44 +00:00
Venkatraman Govindaraju
bb48cf7681 [Sparc] Add fcmpe* instructions to Sparc backend.
llvm-svn: 202661
2014-03-02 19:56:19 +00:00
Venkatraman Govindaraju
13d3f28f34 [Sparc] Add VIS instructions to sparc backend.
llvm-svn: 202660
2014-03-02 19:31:21 +00:00
Venkatraman Govindaraju
caf11daede [SparcV9] Adds support for branch on integer register instructions (BPr) and conditional moves on integer register (MOVr/FMOVr).
llvm-svn: 202628
2014-03-02 09:46:56 +00:00
Venkatraman Govindaraju
e478c48fa6 [Sparc] Add support for parsing branches and conditional move instructions with %fcc1-%fcc3 conditional registers.
llvm-svn: 202616
2014-03-02 06:28:15 +00:00
Venkatraman Govindaraju
6aea38dc6d [Sparc] Add support for parsing fcmp with %fcc registers.
llvm-svn: 202610
2014-03-02 03:39:39 +00:00
Venkatraman Govindaraju
1c2ec775cb [SparcV9] Add support for parsing branch instructions with prediction.
llvm-svn: 202602
2014-03-01 22:03:07 +00:00
Venkatraman Govindaraju
44a4d4b894 [Sparc] Add support for parsing annulled branch instructions.
llvm-svn: 202599
2014-03-01 20:08:48 +00:00
Venkatraman Govindaraju
30d1614f94 [Sparc] Add support for parsing sparcv9 instructions addc/subc/addccc/subccc.
llvm-svn: 202598
2014-03-01 18:54:52 +00:00
Venkatraman Govindaraju
96169e7898 [Sparc] Add missing ALU instruction patterns.
llvm-svn: 202597
2014-03-01 17:51:00 +00:00
Sasa Stankovic
e04070bf23 Add missing FileCheck in test command line.
llvm-svn: 202594
2014-03-01 16:14:29 +00:00
Venkatraman Govindaraju
9a36f7b46b [Sparc] Add support to decode unimp instruction.
llvm-svn: 202581
2014-03-01 09:28:18 +00:00
Venkatraman Govindaraju
043ff79772 [Sparc] Add support to decode negative simm13 operands in the sparc disassembler.
llvm-svn: 202578
2014-03-01 09:11:57 +00:00
Venkatraman Govindaraju
fcbe857272 [Sparc] Add support for decoding call instructions in the sparc disassembler.
llvm-svn: 202577
2014-03-01 08:30:58 +00:00
Venkatraman Govindaraju
1eb4e172be [Sparc] Add support to disassemble sparc memory instructions.
llvm-svn: 202575
2014-03-01 07:46:33 +00:00
Venkatraman Govindaraju
78e98664c7 Add support for parsing sun-style section flags in ELFAsmParser.
llvm-svn: 202573
2014-03-01 06:21:00 +00:00
Venkatraman Govindaraju
9242ded302 [Sparc] Implement writeNopData. Emit actual NOP instruction instead of just filling with zeroes.
llvm-svn: 202572
2014-03-01 05:45:09 +00:00
Venkatraman Govindaraju
dd81a65959 [Sparc] Teach SparcAsmParser to emit correct relocations for PIC code.
llvm-svn: 202571
2014-03-01 05:07:21 +00:00
Venkatraman Govindaraju
789e2fd1b7 [Sparc] Add support for parsing directives in SparcAsmParser.
llvm-svn: 202564
2014-03-01 02:18:04 +00:00
Venkatraman Govindaraju
439a7d90a6 [Sparc] Emit 'restore' instead of 'restore %g0, %g0, %g0'. This improves the readability of the generated code.
llvm-svn: 202563
2014-03-01 01:04:26 +00:00
Zoran Jovanovic
ebb68d0712 Fixed encoding of SYSCALL microMIPS instruction.
llvm-svn: 202523
2014-02-28 18:17:08 +00:00
Zoran Jovanovic
d914bd8ae2 Revert revision 202518 because of wrong commit message.
llvm-svn: 202521
2014-02-28 18:14:16 +00:00
Zoran Jovanovic
43ca53260b Fix operand of SC instruction.
llvm-svn: 202518
2014-02-28 18:02:17 +00:00
Sasa Stankovic
b0018b8bdb [mips] Implement NaCl sandboxing of indirect jumps:
* Align targets of indirect jumps to instruction bundle boundaries (in MI layer).
  * Add masking instructions before indirect jumps (in MC layer).

Differential Revision: http://llvm-reviews.chandlerc.com/D2847

llvm-svn: 202479
2014-02-28 10:00:38 +00:00