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Commit Graph

74 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
7bdae32bfd Remove the SubRegClasses field from RegisterClass descriptions.
This information in now computed by TableGen.

llvm-svn: 156152
2012-05-04 03:30:34 +00:00
Sirish Pande
253d16b1b0 Support for target dependent Hexagon VLIW packetizer.
This patch creates and optimizes packets as per Hexagon ISA rules.

llvm-svn: 156109
2012-05-03 21:52:53 +00:00
Sirish Pande
450a68c937 Extensions of Hexagon V4 instructions.
This adds new instructions for Hexagon V4 architecture.

llvm-svn: 156071
2012-05-03 16:18:50 +00:00
Bill Wendling
003b1bf46c Change the PassManager from a reference to a pointer.
The TargetPassManager's default constructor wants to initialize the PassManager
to 'null'. But it's illegal to bind a null reference to a null l-value. Make the
ivar a pointer instead.
PR12468

llvm-svn: 155902
2012-05-01 08:27:43 +00:00
Preston Gurd
0a730de3c3 This patch fixes a problem which arose when using the Post-RA scheduler
on X86 Atom. Some of our tests failed because the tail merging part of
the BranchFolding pass was creating new basic blocks which did not
contain live-in information. When the anti-dependency code in the Post-RA
scheduler ran, it would sometimes rename the register containing
the function return value because the fact that the return value was
live-in to the subsequent block had been lost. To fix this, it is necessary
to run the RegisterScavenging code in the BranchFolding pass.

This patch makes sure that the register scavenging code is invoked
in the X86 subtarget only when post-RA scheduling is being done.
Post RA scheduling in the X86 subtarget is only done for Atom.

This patch adds a new function to the TargetRegisterClass to control
whether or not live-ins should be preserved during branch folding.
This is necessary in order for the anti-dependency optimizations done
during the PostRASchedulerList pass to work properly when doing
Post-RA scheduling for the X86 in general and for the Intel Atom in particular.

The patch adds and invokes the new function trackLivenessAfterRegAlloc()
instead of using the existing requiresRegisterScavenging().
It changes BranchFolding.cpp to call trackLivenessAfterRegAlloc() instead of
requiresRegisterScavenging(). It changes the all the targets that
implemented requiresRegisterScavenging() to also implement
trackLivenessAfterRegAlloc().  

It adds an assertion in the Post RA scheduler to make sure that post RA
liveness information is available when it is needed.

It changes the X86 break-anti-dependencies test to use –mcpu=atom, in order
to avoid running into the added assertion.

Finally, this patch restores the use of anti-dependency checking
(which was turned off temporarily for the 3.1 release) for
Intel Atom in the Post RA scheduler.

Patch by Andy Zhang!

Thanks to Jakob and Anton for their reviews.

llvm-svn: 155395
2012-04-23 21:39:35 +00:00
Chandler Carruth
9460759e4f Revert r155365, r155366, and r155367. All three of these have regression
test suite failures. The failures occur at each stage, and only get
worse, so I'm reverting all of them.

Please resubmit these patches, one at a time, after verifying that the
regression test suite passes. Never submit a patch without running the
regression test suite.

llvm-svn: 155372
2012-04-23 18:25:57 +00:00
Sirish Pande
9f4844f7da Hexagon V5 (floating point) support.
llvm-svn: 155367
2012-04-23 17:49:40 +00:00
Sirish Pande
4bcbe40295 Support for Hexagon architectural feature, new value jump.
llvm-svn: 155366
2012-04-23 17:49:28 +00:00
Sirish Pande
2230f1957e Support for Hexagon VLIW Packetizer.
llvm-svn: 155365
2012-04-23 17:49:20 +00:00
NAKAMURA Takumi
a5df77be2f llvm/lib/Target: [PR12611] Add "llvm/Support/raw_ostream.h" for Debug build on MSVC.
Thanks to Andy Gibbs, to report the issue.

llvm-svn: 155287
2012-04-21 15:31:45 +00:00
NAKAMURA Takumi
8de1f2e9c7 HexagonISelLowering.cpp: Reorder #includes.
llvm-svn: 155286
2012-04-21 15:31:36 +00:00
NAKAMURA Takumi
64df5a26b4 HexagonInstPrinter.cpp: Suppress -Wunused-variable warnings with -Asserts.
llvm-svn: 155281
2012-04-21 11:24:55 +00:00
Craig Topper
90d95a9142 Convert more uses of XXXRegisterClass to &XXXRegClass. No functional change since they are equivalent.
llvm-svn: 155188
2012-04-20 07:30:17 +00:00
Chandler Carruth
090e90a242 This reverts a long string of commits to the Hexagon backend. These
commits have had several major issues pointed out in review, and those
issues are not being addressed in a timely fashion. Furthermore, this
was all committed leading up to the v3.1 branch, and we don't need piles
of code with outstanding issues in the branch.

It is possible that not all of these commits were necessary to revert to
get us back to a green state, but I'm going to let the Hexagon
maintainer sort that out. They can recommit, in order, after addressing
the feedback.

Reverted commits, with some notes:

Primary commit r154616: HexagonPacketizer
  - There are lots of review comments here. This is the primary reason
    for reverting. In particular, it introduced large amount of warnings
    due to a bad construct in tablegen.
  - Follow-up commits that should be folded back into this when
    reposting:
    - r154622: CMake fixes
    - r154660: Fix numerous build warnings in release builds.
  - Please don't resubmit this until the three commits above are
    included, and the issues in review addressed.

Primary commit r154695: Pass to replace transfer/copy ...
  - Reverted to minimize merge conflicts. I'm not aware of specific
    issues with this patch.

Primary commit r154703: New Value Jump.
  - Primarily reverted due to merge conflicts.
  - Follow-up commits that should be folded back into this when
    reposting:
    - r154703: Remove iostream usage
    - r154758: Fix CMake builds
    - r154759: Fix build warnings in release builds
  - Please incorporate these fixes and and review feedback before
    resubmitting.

Primary commit r154829: Hexagon V5 (floating point) support.
  - Primarily reverted due to merge conflicts.
  - Follow-up commits that should be folded back into this when
    reposting:
    - r154841: Remove unused variable (fixing build warnings)

There are also accompanying Clang commits that will be reverted for
consistency.

llvm-svn: 155047
2012-04-18 21:31:19 +00:00
David Blaikie
61910e5c8e Remove unused variable
llvm-svn: 154841
2012-04-16 18:10:13 +00:00
Sirish Pande
051c2d4395 Hexagon V5 (Floating Point) Support.
llvm-svn: 154829
2012-04-16 17:05:06 +00:00
NAKAMURA Takumi
0133680b3d HexagonCopyToCombine.cpp: Silence two warnings, -Wunused-variable, with -Asserts.
llvm-svn: 154759
2012-04-15 05:33:43 +00:00
NAKAMURA Takumi
ddf2dc407e Target/Hexagon: Tweak to fix msvc build.
llvm-svn: 154758
2012-04-15 05:09:09 +00:00
Sirish Pande
fc7e619733 Remove iostream from New Value Jump.
llvm-svn: 154703
2012-04-13 21:01:35 +00:00
Sirish Pande
6c3fc0ca53 Add support for Hexagon Architectural feature, New Value Jump.
llvm-svn: 154696
2012-04-13 20:22:31 +00:00
Sirish Pande
01b53a9593 Pass to replace tranfer/copy instructions into combine instruction where possible.
llvm-svn: 154695
2012-04-13 20:22:19 +00:00
Craig Topper
7c0af9b204 Silence various build warnings from Hexagon backend that show up in release builds. Mostly converting 'assert(0)' to 'llvm_unreachable' to silence warnings about missing returns. Also fold some variable declarations into asserts to prevent the variables from being unused in release builds.
llvm-svn: 154660
2012-04-13 06:38:11 +00:00
Ted Kremenek
de82fd5282 Update CMake build.
llvm-svn: 154622
2012-04-12 22:15:23 +00:00
Evandro Menezes
dcd4bebf98 Hexagon: fix CMake error.
llvm-svn: 154620
2012-04-12 21:44:58 +00:00
Sirish Pande
ff74c0b4e8 HexagonPacketizer patch.
llvm-svn: 154616
2012-04-12 21:06:38 +00:00
Evandro Menezes
f199e6b61f Hexagon: enable assembler output through the MC layer.
llvm-svn: 154597
2012-04-12 17:55:53 +00:00
Craig Topper
bf6a47d0ec Prune some includes
llvm-svn: 153502
2012-03-27 07:54:11 +00:00
Craig Topper
a2a674effc Remove some unnecessary forward declarations.
llvm-svn: 153245
2012-03-22 06:52:14 +00:00
Craig Topper
b1f171a213 Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations.
llvm-svn: 152997
2012-03-17 18:46:09 +00:00
Craig Topper
bb72c24507 Fix some copy and paste remnants of Cell and SPU in Hexagon files.
llvm-svn: 152981
2012-03-17 09:39:20 +00:00
Craig Topper
41786f284d Fix typo in file header.
llvm-svn: 152980
2012-03-17 09:28:37 +00:00
Craig Topper
3d39a3e5ba Pass TargetOptions to HexagonTargetMachine constructor by reference to match other targets and the base class.
llvm-svn: 152979
2012-03-17 09:24:09 +00:00
Craig Topper
df2bf795d6 Convert more static tables of registers used by calling convention to uint16_t to reduce space.
llvm-svn: 152538
2012-03-11 07:57:25 +00:00
Craig Topper
a95d527c6a Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce static data size.
llvm-svn: 152016
2012-03-05 05:37:41 +00:00
Craig Topper
8cc9d75c6a Use uint16_t to store register overlaps to reduce static data.
llvm-svn: 152001
2012-03-04 10:43:23 +00:00
Craig Topper
585b4225c3 Use uint16_t to store registers in callee saved register tables to reduce size of static data.
llvm-svn: 151996
2012-03-04 03:33:22 +00:00
Evan Cheng
c5ead6c49e Re-commit r151623 with fix. Only issue special no-return calls if it's a direct call.
llvm-svn: 151645
2012-02-28 18:51:51 +00:00
Daniel Dunbar
b448d31a6b Revert r151623 "Some ARM implementaions, e.g. A-series, does return stack prediction. ...", it is breaking the Clang build during the Compiler-RT part.
llvm-svn: 151630
2012-02-28 15:36:07 +00:00
Evan Cheng
d29a22e4b0 Some ARM implementaions, e.g. A-series, does return stack prediction. That is,
the processor keeps a return addresses stack (RAS) which stores the address
and the instruction execution state of the instruction after a function-call
type branch instruction.

Calling a "noreturn" function with normal call instructions (e.g. bl) can
corrupt RAS and causes 100% return misprediction so LLVM should use a
unconditional branch instead. i.e.
mov lr, pc
b _foo
The "mov lr, pc" is issued in order to get proper backtrace.

rdar://8979299

llvm-svn: 151623
2012-02-28 06:42:03 +00:00
Evandro Menezes
aa5e01bb84 Delete incorrect reference to inexistent Hexagon architecture manuals.
llvm-svn: 151582
2012-02-27 23:00:52 +00:00
Craig Topper
9d9d92eab0 Remove HexagonGenIntrinsics.inc from Hexagon cmake file. It does not appear in the Makefile and the output it produces isn't used. The Hexagon intrinsics are all in the global Intrinsics.gen.
llvm-svn: 151514
2012-02-27 02:59:43 +00:00
Benjamin Kramer
62ed7b9b09 Remove unused cl::opt, make another opt static.
llvm-svn: 151398
2012-02-24 22:09:25 +00:00
Brendon Cahoon
0f7dc15d51 Fix the numbering of some of the registers and reclassify a couple of them.
Also, some basic clean up.  Patch by Evandro Menezes.

llvm-svn: 151266
2012-02-23 18:17:17 +00:00
Sirish Pande
5df82d1745 Efficient pattern for store truncate. Patch by Evandro Menezes.
llvm-svn: 151166
2012-02-22 16:45:10 +00:00
Jia Liu
b077b6085d Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
llvm-svn: 150878
2012-02-18 12:03:15 +00:00
Sirish Pande
23474e10dd Optimize redundant sign extends and negation of predicates.
llvm-svn: 150606
2012-02-15 18:52:27 +00:00
Eric Christopher
af0db56b59 Revert "Replacing HexagonOptimizeSZExtends with HexagonPeephole."
This reverts commit 1656806a944bbd23e98c6e578810fe02495ab741.

llvm-svn: 150605
2012-02-15 18:34:25 +00:00
Eric Christopher
559b3c028e Revert "Optimize redundant sign extends and negation of predicates"
as it's breaking the build.

This reverts commit 11241abca5e2a313412fed594bb9d9fa2a2057fb.

llvm-svn: 150604
2012-02-15 18:32:25 +00:00
Sirish Pande
d38fdea9e6 Replacing HexagonOptimizeSZExtends with HexagonPeephole.
llvm-svn: 150603
2012-02-15 18:31:35 +00:00
Sirish Pande
7c661be429 Optimize redundant sign extends and negation of predicates
llvm-svn: 150601
2012-02-15 18:22:18 +00:00