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Commit Graph

185724 Commits

Author SHA1 Message Date
Amara Emerson
bcfd2edd61 Add an operand to memory intrinsics to denote the "tail" marker.
We need to propagate this information from the IR in order to be able to safely
do tail call optimizations on the intrinsics during legalization. Assuming
it's safe to do tail call opt without checking for the marker isn't safe because
the mem libcall may use allocas from the caller.

This adds an extra immediate operand to the end of the intrinsics and fixes the
legalizer to handle it.

Differential Revision: https://reviews.llvm.org/D68151

llvm-svn: 373140
2019-09-28 05:33:21 +00:00
Matt Arsenault
c982aa7a0b AMDGPU/GlobalISel: Avoid getting MRI in every function
Store it in AMDGPUInstructionSelector to avoid boilerplate in nearly
every select function.

llvm-svn: 373139
2019-09-28 03:41:13 +00:00
Craig Topper
666a1a40ae [X86] Add broadcast load unfolding support for VPTESTMD/Q and VPTESTNMD/Q.
llvm-svn: 373138
2019-09-28 01:56:36 +00:00
Craig Topper
e3b69f4175 [X86] Stop using UpdateNodeOperands in combineGatherScatter. Create new nodes like most other DAG combines.
Creating new nodes is what we usually do. Have to explicitly
check that we don't update to an existing node and having
to manually manage the worklist is unusual.

We can probably add a helper function to reduce the duplication
of having to check if we should create a gather or scatter, but
I wanted to just get the simple thing done.

llvm-svn: 373137
2019-09-28 01:08:46 +00:00
Craig Topper
a379ee1929 [X86] Split combineGatherScatter into a version for generic ISD nodes and another version for X86 specific nodes.
The majority of the code doesn't run on the X86 nodes today since
its gated by isBeforeLegalizeOps and we don't formm X86 nodes
until after that. Except for a couple special case in type
legalization. But I think we would probably break those if
some of the transforms fire on them.

I want to remove the hardcoded operand numbers and the unusual
use of UpdateNodeOperands. Being able to know which ISD opcodes
are present should help with that.

llvm-svn: 373136
2019-09-28 01:06:58 +00:00
Wei Mi
dd45f5f726 [SampleFDO] Create a separate flag profile-accurate-for-symsinlist to handle
profile symbol list.

Currently many existing users using profile-sample-accurate want to reduce
code size as much as possible. Their use cases are different from the scenario
profile symbol list tries to handle -- the major motivation of adding profile
symbol list is to get the major memory/code size saving without introduce
performance regression. So to keep the behavior of profile-sample-accurate
unchanged, we think decoupling these two things and using a new flag to
control the handling of profile symbol list may be better.

When profile-sample-accurate and the new flag profile-accurate-for-symsinlist
are both present, since profile-sample-accurate is a user assertion we let it
have a higher precedence.

Differential Revision: https://reviews.llvm.org/D68047

llvm-svn: 373133
2019-09-27 22:33:59 +00:00
Alexander Shaposhnikov
5d5e87b41e [llvm-lipo] Add support for -arch
Add support for -arch.

Differential revision: https://reviews.llvm.org/D68116

Test plan: make check-all

llvm-svn: 373132
2019-09-27 22:33:18 +00:00
Craig Topper
59afa86678 [X86] Add test case to show missed opportunity to turn (add (zext (vXi1 X)), Y) -> (sub Y, (sext (vXi1 X))) with avx512.
With avx512, the vXi1 type is legal. And we can more easily sign
extend them to vector registers. zext requires a sign extend and
a shift.

If we can easily turn the zext into a sext we should.

llvm-svn: 373131
2019-09-27 22:30:24 +00:00
Roman Lebedev
13a563c646 [PatternMatch] Add m_SExtOrSelf(), m_ZExtOrSExtOrSelf() matchers + unittests
m_SExtOrSelf() is for consistency.

m_ZExtOrSExtOrSelf() is motivated by the D68103/r373106 :
sometimes it is useful to look past any extensions of the shift amount,
and m_ZExtOrSExtOrSelf() may be exactly the tool to do that.

llvm-svn: 373128
2019-09-27 21:53:04 +00:00
Yi Kong
f7a791d80b [llvm-readobj] Rename --arm-attributes to --arch-specific
This is for compatibility with GNU readobj. --arm-attributes option is
left as a hidden alias due to large number of tests using it.

Differential Revision: https://reviews.llvm.org/D68110

llvm-svn: 373125
2019-09-27 20:38:18 +00:00
Sanjay Patel
31f480507c [InstSimplify] generalize FP folds with undef/NaN; NFC
We can reuse this logic for things like fma.

llvm-svn: 373119
2019-09-27 20:09:09 +00:00
Jakub Kuderski
3bff328a07 Revert [Dominators][CodeGen] Clean up MachineDominators
This reverts r373101 (git commit 72c57ec3e6b320c31274dadb888dc16772b8e7b6)

llvm-svn: 373117
2019-09-27 19:33:39 +00:00
Jakub Kuderski
a411fb008a Revert XFAIL a codegen test AArch64/tailmerging_in_mbp.ll
This reverts r373103 (git commit a524e630a793e18e7d5fabc2262781f310eb0279)

llvm-svn: 373116
2019-09-27 19:33:35 +00:00
Roman Lebedev
7229fdbc81 [NFC][PhaseOrdering] Add end-to-end tests for the 'two shifts by sext' problem
We start with two separate sext's, but EarlyCSE runs before InstCombine,
so when we get them, they are a single sext, and we just ignore that.
Likewise, if we had a single sext, we don't do anything there.

llvm-svn: 373115
2019-09-27 19:32:43 +00:00
DeForest Richards
e4f8869b72 [Docs] Adds new section to User Guides page
Adds a section to the User Guides page for articles related to building, packaging, and distributing LLVM. Includes sub-sections for CMake, Clang, and Docker.

llvm-svn: 373113
2019-09-27 19:12:00 +00:00
Sanjay Patel
58281c58fc [InstSimplify] add tests for fma/fmuladd with undef operand; NFC
llvm-svn: 373109
2019-09-27 18:38:51 +00:00
Craig Topper
db855efbed [X86] Call SimplifyDemandedBits in combineGatherScatter any time the mask element is wider than i1, not just when AVX512 is disabled.
The AVX2 intrinsics can still be used when AVX512 is enabled and
those go through this path. So we should simplify them.

llvm-svn: 373108
2019-09-27 18:23:55 +00:00
Craig Topper
a2a144c550 [X86] Add test case to show failure to perform SimplifyDemandedBits on mask of avx2 gather intrinsics when avx512 is enabled.
llvm-svn: 373107
2019-09-27 18:23:46 +00:00
Roman Lebedev
120da12eeb [InstCombine] Simplify shift-by-sext to shift-by-zext
Summary:
This is valid for any `sext` bitwidth pair:
```
Processing /tmp/opt.ll..

----------------------------------------
  %signed = sext %y
  %r = shl %x, %signed
  ret %r
=>
  %unsigned = zext %y
  %r = shl %x, %unsigned
  ret %r
  %signed = sext %y

Done: 2016
Optimization is correct!
```

(This isn't so for funnel shifts, there it's illegal for e.g. i6->i7.)

Main motivation is the C++ semantics:
```
int shl(int a, char b) {
    return a << b;
}
```
ends as
```
  %3 = sext i8 %1 to i32
  %4 = shl i32 %0, %3
```
https://godbolt.org/z/0jgqUq
which is, as this shows, too pessimistic.

There is another problem here - we can only do the fold
if sext is one-use. But we can trivially have cases
where several shifts have the same sext shift amount.
This should be resolved, later.

Reviewers: spatel, nikic, RKSimon

Reviewed By: spatel

Subscribers: efriedma, hiraditya, nlopes, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D68103

llvm-svn: 373106
2019-09-27 18:12:15 +00:00
Jakub Kuderski
610e2b3c9d XFAIL a codegen test AArch64/tailmerging_in_mbp.ll
This test fails when machine dominator tree verifier is run.
Needs more investigation, as this is not a new failure.

llvm-svn: 373103
2019-09-27 17:41:17 +00:00
Jakub Kuderski
040d8dbfa9 [Dominators][CodeGen] Clean up MachineDominators
Summary: This is a cleanup patch for MachineDominatorTree. It would be an NFC, except for replacing custom DomTree verification with the generic one.

Reviewers: tstellar, tpr, nhaehnle, arsenm, NutshellySima, grosser, hliao

Reviewed By: arsenm

Subscribers: wdng, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67976

llvm-svn: 373101
2019-09-27 17:25:39 +00:00
Simon Pilgrim
434994afd7 Fix MSVC "not all control paths return a value" warning. NFCI.
llvm-svn: 373100
2019-09-27 16:56:07 +00:00
Simon Pilgrim
d0072a6ced ModuleUtils - silence static analyzer dyn_cast<> null dereference warning. NFCI.
The static analyzer is warning about a potential null dereference, but we should be able to use cast<> directly and if not assert will fire for us.

llvm-svn: 373099
2019-09-27 16:55:49 +00:00
Kai Nacke
b3f72a7ae7 Change -march=systemz to triple and fix test
These two test cases use -march=systemz instead of a triple. In
particular, the used file format is then based on the default host
triple. This leads to different behaviour on different platforms.

The SystemZ implementation uses the integrated assembler for a
long time now. The mature-mc-support test can be fully enabled.

Differential Revision: https://reviews.llvm.org/D68129

llvm-svn: 373098
2019-09-27 16:19:15 +00:00
Simon Pilgrim
763eac1a90 FunctionImportGlobalProcessing::processGlobalForThinLTO - silence static analyzer dyn_cast<FunctionSummary> null dereference warning. NFCI.
The static analyzer is warning about a potential null dereference, but we should be able to use cast<FunctionSummary> directly and if not assert will fire for us.

llvm-svn: 373097
2019-09-27 15:49:19 +00:00
Luis Marques
bc3e25486a [RISCV] Rename FPRs and use Register arithmetic
The new names for FPRs ensure that the Register values within the same class are
enumerated consecutively (the order is determined by the `LessRecordRegister`
function object). Where there were tables mapping between 32- and 64-bit FPRs
(and vice versa) this patch replaces them with Register arithmetic. The
enumeration order between different register classes is expected to continue to
be arbitrary, although it does impact the conversion from the (overloaded) asm
FPR names to Register values, and therefore might require updates to the target
if the sorting algorithm is changed. Static asserts were added to ensure that
changes to the ordering that would impact the current implementation are
detected.

Differential Revision: https://reviews.llvm.org/D67423

llvm-svn: 373096
2019-09-27 15:49:10 +00:00
Simon Pilgrim
a9e2380a5d SCCP - silence static analyzer dyn_cast<StructType> null dereference warning. NFCI.
The static analyzer is warning about a potential null dereference, but we should be able to use cast<StructType> directly and if not assert will fire for us.

llvm-svn: 373095
2019-09-27 15:49:10 +00:00
Dmitry Preobrazhensky
09506da3e3 [AMDGPU][MC] Corrected parsing of registers
Summary of changes:

refactored code for better readability and future improvements;
fixed bug 41281: https://bugs.llvm.org/show_bug.cgi?id=41281

Reviewers: artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D65224

llvm-svn: 373094
2019-09-27 15:41:31 +00:00
Djordje Todorovic
7c429fc379 [DebugInfo] Exclude memory location values as parameter entry values
Abandon describing of loaded values due to safety concerns. Loaded
values are described as derefed memory location at caller point.
At callee we can unintentionally change that memory location which
would lead to different entry being printed value before and after
the memory location clobbering. This problem is described in
llvm.org/PR43343.

Patch by Nikola Prica

Differential Revision: https://reviews.llvm.org/D67717

llvm-svn: 373089
2019-09-27 13:52:43 +00:00
Clement Courbet
8a234db13c [llvm-exegesis] Fix r373083: Module -> Mod.
SnippetRepetitorTest.cpp:66:27: error: declaration of ‘std::unique_ptr<llvm::Module> llvm::exegesis::{anonymous}::X86SnippetRepetitorTest::Module’ [-fpermissive]
   std::unique_ptr<Module> Module;

llvm-svn: 373087
2019-09-27 13:21:37 +00:00
Nico Weber
953858a81d gn build: (manually) merge r373082
llvm-svn: 373086
2019-09-27 13:14:34 +00:00
GN Sync Bot
7ca190b53d gn build: Merge r373083
llvm-svn: 373085
2019-09-27 13:04:46 +00:00
Jesper Antonsson
9125982a28 [CodeGenPrepare] Mend "avoid crashing from replacing a phi twice" fix.
Summary:
An erroneously negated if-statement by an earlier (March 2019) bugfix left phi replacement/simplification under optimizeMemoryInst()  in CodeGenPrepare largely inactivated. The error was found when csmith found that the same assert as in the original bug report could still be triggered in a different way. This patch fixes the bugfix. The original bug was:
 https://bugs.llvm.org/show_bug.cgi?id=41052
... and the previous fix was D59358.

Reviewers: aprantl, skatkov

Reviewed By: skatkov

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67838

llvm-svn: 373084
2019-09-27 13:01:37 +00:00
Clement Courbet
9c2e0e0fa4 [llvm-exegesis] Add loop mode for repeating the snippet.
Summary:
Before this change the Executable function was made by duplicating the
snippet. This change adds a --repetion-mode={loop|duplicate} flag that
allows choosing between this behaviour and wrapping the snippet instructions
in a loop.

The new mode can help measurements when the snippet fits in the DSB by
short-cirtcuiting decoding. The loop adds a dec + jmp to the measurements, but
since these are not part of the critical path, they execute in parallel
with the measured code and do not impact measurements in practice.

Overview of the change:
 - New SnippetRepetitor abstraction that handles repeating the snippet.
   The assembler delegates repeating the instructions to this class.
 - ExegesisTarget learns how to decrement loop counter and jump.
 - Some refactoring of the assembler into FunctionFiller/BasicBlockFiller.

Reviewers: gchatelet

Subscribers: mgorny, tschuett, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D68125

llvm-svn: 373083
2019-09-27 12:56:24 +00:00
Guillaume Chatelet
114e854bc6 [Alignment][NFC] Remove unneeded llvm:: scoping on Align types
llvm-svn: 373081
2019-09-27 12:54:21 +00:00
Nico Weber
6a8ef0b7b3 Reland "gn build: (manually) merge r373028"
This relands r373029, reverted in 373033, because r373028 relanded in r373066.

llvm-svn: 373070
2019-09-27 11:37:59 +00:00
Sam Parker
e8556a8898 [NFC][ARM] Add some tail-predication tests
Use different data types for some simple loops.

llvm-svn: 373064
2019-09-27 10:33:53 +00:00
Simon Pilgrim
85979f36a0 [SLPVectorizer][X86] Regenerate arith-fp tests
llvm-svn: 373063
2019-09-27 10:04:25 +00:00
Simon Pilgrim
9314ff93e0 [UpdateTestChecks] Fix wildcard support on DOS prompts
D64572 / rL365818 changed the way that the file paths were collected, which meant we lost the file pattern expansion necessary when working with DOS command prompt

llvm-svn: 373062
2019-09-27 10:04:16 +00:00
Hans Wennborg
e727b1924f Revert r372893 "[CodeGen] Replace -max-jump-table-size with -max-jump-table-targets"
This caused severe compile-time regressions, see PR43455.

> Modern processors predict the targets of an indirect branch regardless of
> the size of any jump table used to glean its target address.  Moreover,
> branch predictors typically use resources limited by the number of actual
> targets that occur at run time.
>
> This patch changes the semantics of the option `-max-jump-table-size` to limit
> the number of different targets instead of the number of entries in a jump
> table.  Thus, it is now renamed to `-max-jump-table-targets`.
>
> Before, when `-max-jump-table-size` was specified, it could happen that
> cluster jump tables could have targets used repeatedly, but each one was
> counted and typically resulted in tables with the same number of entries.
> With this patch, when specifying `-max-jump-table-targets`, tables may have
> different lengths, since the number of unique targets is counted towards the
> limit, but the number of unique targets in tables is the same, but for the
> last one containing the balance of targets.
>
> Differential revision: https://reviews.llvm.org/D60295

llvm-svn: 373060
2019-09-27 09:54:26 +00:00
Thomas Preud'homme
1349d8564d [sancov][NFC] Make filename Regexes "const"
Summary:
The const-correctness of match() was fixed in rL372764, which allows
such static Regex objects to be marked const.

Reviewers: thopre

Reviewed By: thopre

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D68091

llvm-svn: 373058
2019-09-27 09:39:13 +00:00
Roman Lebedev
c09b37c168 [NFC][InstCombine] Revisit shift-by-signext tests
llvm-svn: 373055
2019-09-27 09:09:15 +00:00
Guillaume Chatelet
7c8bc22ca6 [Alignment][NFC] MaybeAlign in GVNExpression
Summary:
This is patch is part of a series to introduce an Alignment type.
See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html
See this patch for the introduction of the type: https://reviews.llvm.org/D64790

Reviewers: courbet

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D67922

llvm-svn: 373054
2019-09-27 08:56:43 +00:00
Alexandros Lamprineas
67cf4fb1cb [MC][ARM] vscclrm disassembles as vldmia
Happens only when the mve.fp subtarget feature is enabled:

$ llvm-mc -triple thumbv8.1m.main -mattr=+mve.fp,+8msecext -disassemble <<< "0x9f,0xec,0x08,0x0b"
  .text
  vldmia  pc, {d0, d1, d2, d3}
$ llvm-mc -triple thumbv8.1m.main -mattr=+8msecext -disassemble <<< "0x9f,0xec,0x08,0x0b"
  .text
  vscclrm {d0, d1, d2, d3, vpr}

Assembling returns the correct encoding with or without mve.fp:

$ llvm-mc -triple thumbv8.1m.main -mattr=+mve.fp,+8msecext -show-encoding <<< "vscclrm {d0-d3, vpr}"
  .text
  vscclrm {d0, d1, d2, d3, vpr}   @ encoding: [0x9f,0xec,0x08,0x0b]
$ llvm-mc -triple thumbv8.1m.main -mattr=+8msecext -show-encoding <<< "vscclrm {d0-d3, vpr}"
  .text
  vscclrm {d0, d1, d2, d3, vpr}   @ encoding: [0x9f,0xec,0x08,0x0b]

The problem seems to be in the TableGen description of VSCCLRMD.
The least significant bit should be set to zero.

Differential Revision: https://reviews.llvm.org/D68025

llvm-svn: 373052
2019-09-27 08:22:24 +00:00
Clement Courbet
e063a909a2 [llvm-exegesis] Refactor how forbidden registers are computed.
Summary:
Right now latency generation can incorrectly select the scratch register
as a dependency-carrying register.
 - Move the logic for preventing register selection from Uops
   implementation to common SnippetGenerator class.
 - Aliasing detection now takes a set of forbidden registers just like
   random register assignment does.

Reviewers: gchatelet

Subscribers: tschuett, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D68084

llvm-svn: 373048
2019-09-27 08:04:10 +00:00
Wei Mi
e03a35d303 [LoopInfo] Remove duplicates in ExitBlocks to reduce the compile time of
hasDedicatedExits.

For the compile time problem described in https://reviews.llvm.org/D67359,
turns out the root cause is there are many duplicates in ExitBlocks so
the algorithm complexity of hasDedicatedExits gets very high. If we remove
the duplicates, the compile time issue is gone.

Thanks to Philip Reames for raising a good question and it leads me to
find the root cause.

Differential Revision: https://reviews.llvm.org/D68107

llvm-svn: 373045
2019-09-27 05:43:31 +00:00
Wei Mi
92134e706c Revert "[LoopInfo] Limit the iterations to check whether a loop has dedicated
exits"

Get a better approach in https://reviews.llvm.org/D68107 to solve the problem.
Revert the initial patch and will commit the new one soon.

This reverts commit rL372990.

llvm-svn: 373044
2019-09-27 05:43:30 +00:00
Thomas Lively
6acb2d6fe1 [WebAssembly] v128.andnot
Summary:
As specified at
https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#bitwise-and-not

Reviewers: aheejin

Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D68113

llvm-svn: 373041
2019-09-27 02:11:40 +00:00
Thomas Lively
01ad7e0891 [WebAssembly] SIMD Load and extend operations
Summary:
As specified at
https://github.com/webassembly/simd/blob/master/proposals/simd/SIMD.md#load-and-extend.
These instructions are behind the unimplemented-simd128 target feature
for now because they have not been implemented in V8 yet.

Reviewers: aheejin

Subscribers: dschuff, sbc100, jgravelle-google, hiraditya, sunfish, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D68058

llvm-svn: 373040
2019-09-27 02:06:50 +00:00
Nicholas Allegra
52b783a790 Revert r373034
It breaks the build on MSVC.

llvm-svn: 373039
2019-09-27 01:58:31 +00:00