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Commit Graph

131388 Commits

Author SHA1 Message Date
Simon Pilgrim
0f2ef1de0a Fixed unused but set variable warning
llvm-svn: 268931
2016-05-09 16:42:23 +00:00
Matt Arsenault
f726e32980 AMDGPU: Fold shift into cvt_f32_ubyteN
llvm-svn: 268930
2016-05-09 16:29:50 +00:00
Sanjay Patel
21937246e3 fix spelling; NFC
llvm-svn: 268929
2016-05-09 16:07:45 +00:00
Daniel Sanders
77f004d65f [mips] Try to fix 'truncation from FindBestPredicateResult to bool' reported by MSVC
llvm-svn: 268928
2016-05-09 15:50:15 +00:00
Daniel Sanders
dd90de11d3 [mips][ias] Attempt to fix 'not all control paths return a value' reported by MSVC.
llvm-svn: 268927
2016-05-09 15:37:52 +00:00
Frederic Riss
9572f5c72f [dsymutil] Prevent use-after-free
The BinaryHolder would query the archive member MemoryBuffer name
to check if the current open archive also contains the next requested
objectfile. This comparison was using a StringRef to a temporary
buffer. It only happened with fat archives. This commit adds long-lived
storage along with the MemoryBuffers for the fat archive filename.

The added test would fail during an ASAN build without the fix.

llvm-svn: 268924
2016-05-09 14:44:14 +00:00
Joerg Sonnenberger
30460c8dd2 Optimize a printf with a double procent to putchar.
llvm-svn: 268922
2016-05-09 14:36:16 +00:00
James Molloy
dde84f9cd6 [VectorUtils] Query number of sign bits to allow more truncations
When deciding if a vector calculation can be done in a smaller bitwidth, use sign bit information from ValueTracking to add more information and allow more truncations.

llvm-svn: 268921
2016-05-09 14:32:30 +00:00
Daniel Sanders
76aeb9f378 [mips][micromips] Make getPointerRegClass() result depend on the instruction.
Summary:
Previously, it returned the GPR16MMRegClass for all instructions which was
incorrect for instructions like lwsp/lwgp and unnecesarily restricted the
permitted registers for instructions like lw32.

This fixes quite a few of the -verify-machineinstrs errors reported in PR27458.
I've only added -verify-machineinstrs to one test in this change since I
understand there is a plan to enable the verifier by default.

Reviewers: hvarga, zbuljan, zoran.jovanovic, sdardis

Subscribers: dsanders, llvm-commits, sdardis

Differential Revision: http://reviews.llvm.org/D19873

llvm-svn: 268918
2016-05-09 13:38:25 +00:00
Rafael Espindola
af070e4f0c Fix bug where temporary file would be left behind every time an archive was updated.
When updating an existing archive, llvm-ar opens the old archive into a
`MemoryBuffer`, does its thing, and writes the results to a temporary
file. That file is then renamed to the original archive filename, thus
replacing it with the updated contents. However, on Windows at least,
what would happen is that the `MemoryBuffer` for the old archive would
actually be an mmap'ed view of the file, so when it came time to do the
rename via Win32's `ReplaceFile`, it would succeed but would be unable
to fully replace the file since there would still be a handle open on
it; instead, the old version got renamed to a random temporary name and
left behind.

Patch by Cameron!

llvm-svn: 268916
2016-05-09 13:31:11 +00:00
Simon Pilgrim
3ddc1a30df [X86][SSE] Added TODO comment to add support for AVX512 mask registers to shuffle comments
This came up in discussion on D19198

llvm-svn: 268915
2016-05-09 13:30:16 +00:00
Daniel Sanders
22a6cb21be [mips] Fix use after free and an unnecessary copy introduced in r268896.
llvm-svn: 268913
2016-05-09 13:10:57 +00:00
Strahinja Petrovic
e297a43f7c [PowerPC] fix register alignment for long double type
This patch fixes register alignment for long double type in
soft float mode. Before this patch alignment was 8 and this
patch changes it to 4.
Differential Revision: http://reviews.llvm.org/D18034

llvm-svn: 268909
2016-05-09 12:27:39 +00:00
Chris Dewhurst
9cefba091e [Sparc][LEON] Add UMAC and SMAC instruction support for Sparc LEON subtargets
This change adds SMAC (signed multiply-accumulate) and UMAC (unsigned multiply-accumulate) for LEON subtargets of the Sparc processor.

The new files LeonFeatures.td and leon-instructions.ll will both be expanded in future, so I want to leave them separate as small files for this review, to be expanded in future check-ins.

Note: The functions are provided only for inline-assembly provision. No DAG selection is provided.

Differential Revision: http://reviews.llvm.org/D19911

llvm-svn: 268908
2016-05-09 11:55:15 +00:00
Silviu Baranga
edcf928591 [AArch64] Implement lowering of the X constraint on AArch64
Summary:
This implements the lowering of the X constraint on
AArch64.

The default behaviour of the X constraint lowering is to
restrict it to "f". This is a problem because the "f"
constraint is not implemented on AArch64 and would be too
restrictive anyway. Therefore, the AArch64 hook will
lower this to "w" (if the operand is a floating point or
vector) or "r" otherwise.

The implementation is similar with the one added for
ARM (r267411).

This is the AArch64 side of the fix for http://llvm.org/PR26493

Reviewers: rengolin

Subscribers: aemerson, rengolin, llvm-commits, t.p.northover

Differential Revision: http://reviews.llvm.org/D19967

llvm-svn: 268907
2016-05-09 11:10:44 +00:00
Simon Pilgrim
af9bc1432f [X86][AVX512] Added masked version of combine tests
llvm-svn: 268904
2016-05-09 10:43:13 +00:00
Benjamin Kramer
8779c9c4d8 Revert "[Mips] Fix use after free."
Fixes use after free but breaks tests.

This reverts commit r268901.

llvm-svn: 268902
2016-05-09 10:31:17 +00:00
Benjamin Kramer
5385b15220 [Mips] Fix use after free.
llvm-svn: 268901
2016-05-09 10:21:56 +00:00
Daniel Sanders
828a69bd74 [mips][ias] R_MIPS_(GOT|HI|LO|PC)16 and R_MIPS_GPREL32 do not need symbols.
Summary:
In theory, care must be taken to ensure that pairs of R_MIPS_(GOT|HI|LO)16
make the same decision on both relocs in the reloc pair but in practice
this isn't as hard as it sounds and only limits the complexity of the
predicate used. We handle all three with the same code to ensure their
decisions always agree with each other.

Reviewers: sdardis

Subscribers: rafael, dsanders, sdardis, llvm-commits

Differential Revision: http://reviews.llvm.org/D19016

llvm-svn: 268900
2016-05-09 10:21:14 +00:00
Zlatko Buljan
4c55849feb [mips][microMIPS] Implement LWP and SWP instructions
Differential Revision: http://reviews.llvm.org/D10640

llvm-svn: 268896
2016-05-09 08:07:28 +00:00
Frederic Riss
ca05ea2936 [dsymutil] Fix -arch option for thumb variants.
r267249 removed the dual ARM/Thumb interface from MachOObjectFile,
simplifying llvm-dsymutil's code. This unfortunately also regressed
llvm-dsymutil's ability to select thumb slices, because the simplified
code was also dealing with the discrepency between the slice arch
(eg. armv7m) and the triple arch name (eg. thumbv7m).

llvm-svn: 268894
2016-05-09 06:01:12 +00:00
Craig Topper
f0db9d6006 [X86] Strengthen some type contraints for floating point round and extend.
llvm-svn: 268892
2016-05-09 05:34:14 +00:00
Craig Topper
1a7c59b5bb [AVX512] Fix up types for arguments of int_x86_avx512_mask_cvtsd2ss_round and int_x86_avx512_mask_cvtss2sd_round. Only the argument being converted should be a different type. The other 2 argument should have the same type as the result.
llvm-svn: 268891
2016-05-09 05:34:12 +00:00
Mehdi Amini
5bcf351ca9 ThinLTOCodeGenerator: ignore 0 values for the cache settings.
From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 268890
2016-05-09 05:16:30 +00:00
Craig Topper
79a42b734a [AVX512] Add non-temporal store patterns for v16i32/v32i16/v64i8.
llvm-svn: 268889
2016-05-08 23:43:17 +00:00
Junmo Park
6b5b741b3c Minor code cleanups. NFC.
llvm-svn: 268888
2016-05-08 23:22:58 +00:00
Craig Topper
003ac12540 [AVX512] Add missing patterns for non-temporal stores of 128/256-bit vXi8/vXi16/vXi32 when VLX is enabled. The equivalent AVX1/2 patterns are disabled by VLX.
This caused regular stores to be emitted instead.

llvm-svn: 268886
2016-05-08 23:08:45 +00:00
Craig Topper
b6baa777fe [AVX512] Change predicates on some vXi16/vXi8 AVX store patterns so they stay enabled unless VLX and BWI instructions are supported."
Without this we could fail instruction selection if VLX was enabled, but BWI wasn't.

llvm-svn: 268885
2016-05-08 23:08:40 +00:00
Craig Topper
dd43e37f21 [AVX512] Add VLX 128/256-bit SET0 operations that encode to 128/256-bit EVEX encoded VPXORD so all 32 registers can be used.
llvm-svn: 268884
2016-05-08 21:33:53 +00:00
Craig Topper
c70de22395 [X86] Re-generate tests using update_llc_test_checks.py to prepare for a future commit. NFC
llvm-svn: 268883
2016-05-08 21:33:47 +00:00
Craig Topper
aa912578a2 Remove Windows line endings in some tests to prepare for a future commit. NFC
llvm-svn: 268882
2016-05-08 21:33:44 +00:00
Bruno Cardoso Lopes
9f87bc51d4 [Bitcode] Fix an unsigned integer overflow while parsing bitcode wrapper header
Specially crafted bitcode wrapper headers can cause unsigned interger
overflow and lead to crashes when wrapping around. Fix the offset check
and avoid such scenarios.

Writing a testcase for this would involve editing the binary to generate
values that trigger the overflow, since this would never happen while
generating the bitcode in regular compilation flows, so there's
currently no feasible way add one.

llvm-svn: 268881
2016-05-08 21:27:39 +00:00
Craig Topper
872733a7d7 [X86] Remove extra patterns that check for BUILD_VECTOR of all 0s. These are always canonicalized to v4i32/v8i32/v16i32 except for in SSE1 only when only v4f32 is supported.
llvm-svn: 268880
2016-05-08 20:10:20 +00:00
Simon Pilgrim
f8175826a4 [CostModel][X86] Extended comparison instruction cost model tests to include SSE2/SSE3/SSSE3/SSE41/SSE42 targets
llvm-svn: 268877
2016-05-08 15:24:53 +00:00
David Majnemer
ed9abdfae3 [X86] Promote several single precision FP libcalls on Windows
A number of libcalls don't exist in any particular lib but are, instead,
defined in math.h as inline functions (even in C mode!).  Don't rely on
their existence when lowering @llvm.{cos,sin,floor,..}.f32, promote them
instead.

N.B. We had logic to handle FREM but were missing out on a number of
others.  This change generalizes the FREM handling.

llvm-svn: 268875
2016-05-08 08:15:50 +00:00
Craig Topper
ce30d72448 [X86] Lower 256-bit vector all-zero constants to v8i32 even with AVX1 only. Either way a 256-bit VXORPS will be used.
llvm-svn: 268873
2016-05-08 07:10:54 +00:00
Craig Topper
17e31eeac8 [X86] Add patterns for 256-bit non-temporal stores when only AVX1 is supported. While there, add a predicate to the SSE2 patterns to avoid an ordering dependency.
llvm-svn: 268872
2016-05-08 07:10:50 +00:00
Craig Topper
85b1036796 [X86] No need to avoid selecting AVX_SET0 for 256-bit integer types when only AVX1 is supported. AVX_SET0 just expands to 256-bit VXORPS which is legal in AVX1.
llvm-svn: 268871
2016-05-08 07:10:47 +00:00
Weiming Zhao
b94762d920 [ARM] Fix Scavenger assert due to underestimated stack size
(re-apply r268810 as it exposed an uninitialized variable in ARM MFI.
 Patch 268868 should fix that.)

Summary:
Currently, when checking if a stack is "BigStack" or not, it doesn't count into spills and arguments. Therefore, LLVM won't reserve spill slot for this actually "BigStack". This may cause scavenger failure.

Reviewers: rengolin

Subscribers: vitalybuka, aemerson, rengolin, tberghammer, danalbert, srhines, llvm-commits

Differential Revision: http://reviews.llvm.org/D19896

llvm-svn: 268869
2016-05-08 05:11:54 +00:00
Weiming Zhao
85513d3f4e Fix use-of-uninitialized-value of ARMMachineFunctionInfo
Summary: Explicitly initialize ArgumentStackSize to prevent the msan failure.

Reviewers: rengolin

Subscribers: aemerson, rengolin, llvm-commits

Differential Revision: http://reviews.llvm.org/D20051

llvm-svn: 268868
2016-05-08 05:04:47 +00:00
Simon Pilgrim
f1ce15085b Fix unused variable warning.
llvm-svn: 268867
2016-05-07 20:19:59 +00:00
Simon Pilgrim
2b77907462 [SelectionDAG] Added bitreverse(bitreverse(v)) --> v
Added bitreverse creation testing

llvm-svn: 268865
2016-05-07 20:12:36 +00:00
Craig Topper
7b7547a4dc [X86] Fix InstAliases to not allow FARCALL32i/FARCALL16i/FARJMP32i/FARJMP16i in 64-bit mode.
llvm-svn: 268863
2016-05-07 19:25:56 +00:00
Simon Pilgrim
e9ecfedf2a [X86] Added BITREVERSE constant folding and identity tests
Identity tests are currently failing - this will be fixed soon

llvm-svn: 268862
2016-05-07 19:04:00 +00:00
Simon Pilgrim
ecb5f17d8b [X86] Pulled out duplicate mask width calculation. NFCI.
llvm-svn: 268861
2016-05-07 18:04:24 +00:00
Simon Pilgrim
d0b4e9facb [CostModel][X86] Split BSWAP/BITREVERSE cost tests from CTPOP/CTLZ/CTTZ 'bit count' cost tests
llvm-svn: 268859
2016-05-07 16:34:16 +00:00
Sanjay Patel
64251c0df0 [x86, BMI] add TLI hook for 'andn' and use it to simplify comparisons
For the sake of minimalism, this patch is x86 only, but I think that at least
PPC, ARM, AArch64, and Sparc probably want to do this too.

We might want to generalize the hook and pattern recognition for a target like
PPC that has a full assortment of negated logic ops (orc, nand).

Note that http://reviews.llvm.org/D18842 will cause this transform to trigger
more often.

For reference, this relates to:
https://llvm.org/bugs/show_bug.cgi?id=27105
https://llvm.org/bugs/show_bug.cgi?id=27202
https://llvm.org/bugs/show_bug.cgi?id=27203
https://llvm.org/bugs/show_bug.cgi?id=27328

Differential Revision: http://reviews.llvm.org/D19087

llvm-svn: 268858
2016-05-07 15:03:40 +00:00
NAKAMURA Takumi
0e8e31391d ErrorInfoBase::message(): Don't use raw_string_ostream's buffer, Msg, before closing. Use raw_string_ostream::str() to flush the buffer.
llvm-svn: 268856
2016-05-07 08:43:11 +00:00
Xinliang David Li
423ce480aa [PM] code refactoring -- preparation for new PM porting /NFC
llvm-svn: 268851
2016-05-07 05:39:12 +00:00
Mehdi Amini
24eaf9319e Fix stripDebugInfo: was modifying "DebugLoc" attached to the intrinsic after deleting it.
Fix MSAN build.

From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 268849
2016-05-07 05:07:47 +00:00