2 Commits

Author	SHA1	Message	Date
Hsiangkai Wang	c0d659ef28	[RISCV] Use v8-v23 as argument registers to conform to the proposal. ... The maximum LMUL is 8. We need 16 vector registers for two LMUL-8 arguments. The modification follows the proposal of psABI in https://github.com/riscv/riscv-elf-psabi-doc/pull/171 Differential Revision: https://reviews.llvm.org/D95134	2021-01-22 07:55:24 +08:00
Evandro Menezes	c0ec25ab1b	[RISCV] Define the vfclass RVV intrinsics ... Define the `vfclass` IR intrinsics for the respective V instructions. Authored-by: Roger Ferrer Ibanez <rofirrim@gmail.com> Co-Authored-by: Evandro Menezes <evandro.menezes@sifive.com> Differential Revision: https://reviews.llvm.org/D94356	2021-01-11 17:40:09 -06:00