2 Commits

Author	SHA1	Message	Date
Hsiangkai Wang	c0d659ef28	[RISCV] Use v8-v23 as argument registers to conform to the proposal. ... The maximum LMUL is 8. We need 16 vector registers for two LMUL-8 arguments. The modification follows the proposal of psABI in https://github.com/riscv/riscv-elf-psabi-doc/pull/171 Differential Revision: https://reviews.llvm.org/D95134	2021-01-22 07:55:24 +08:00
Zakk Chen	16ba1c6d5e	[RISCV] Define vsext/vzext intrinsics. ... Define vsext/vzext intrinsics.and lower to V instructions. Define new fraction register class fields in LMULInfo and a NoReg to present invalid LMUL register classes. Authored-by: ShihPo Hung <shihpo.hung@sifive.com> Co-Authored-by: Zakk Chen <zakk.chen@sifive.com> Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D93893	2020-12-29 16:50:53 -08:00