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1087888176
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2415 Commits

Author SHA1 Message Date
Bill Wendling
1087888176 Unbreak mmx arithmetic. It was barfing trying to do v8i8 arithmetic. 
llvm-svn: 35392
 2007-03-28 00:57:11 +00:00
Bill Wendling
6b555c80c0 Add the "unpack low packed data" instructions. This should be the last of 
the MMX instructions that are needed...

llvm-svn: 35389
 2007-03-27 21:20:36 +00:00
Bill Wendling
d43819da2f Fix so that pandn is emitted instead of an xor/and combo. Add integer 
comparison operators.

llvm-svn: 35385
 2007-03-27 20:22:40 +00:00
Bill Wendling
8065cc3173 Promote to v1i64 type... 
llvm-svn: 35353
 2007-03-26 08:03:33 +00:00
Bill Wendling
3c4e130b77 Updated. 
llvm-svn: 35352
 2007-03-26 07:55:58 +00:00
Bill Wendling
a42484728c Add support for the v1i64 type. This makes better code for this: 
#include <mmintrin.h>

extern __m64 C;

void baz(__v2si *A, __v2si *B)
{
  *A = C;
  _mm_empty();
}

We get this:

_baz:
        call "L1$pb"
"L1$pb":
        popl %eax
        movl L_C$non_lazy_ptr-"L1$pb"(%eax), %eax
        movq (%eax), %mm0
        movl 4(%esp), %eax
        movq %mm0, (%eax)
        emms
        ret

GCC gives us this:

_baz:
        pushl   %ebx
        call    L3
"L00000000001$pb":
L3:
        popl    %ebx
        subl    $8, %esp
        movl    L_C$non_lazy_ptr-"L00000000001$pb"(%ebx), %eax
        movl    (%eax), %edx
        movl    4(%eax), %ecx
        movl    16(%esp), %eax
        movl    %edx, (%eax)
        movl    %ecx, 4(%eax)
        emms
        addl    $8, %esp
        popl    %ebx
        ret

llvm-svn: 35351
 2007-03-26 07:53:08 +00:00
Chris Lattner
b19069959d switch TargetLowering::getConstraintType to take the entire constraint, 
not just the first letter.  No functionality change.

llvm-svn: 35322
 2007-03-25 02:14:49 +00:00
Chris Lattner
18c3c6a01d Allow the b/h/w/k constraints to be applied to values that have multiple alternatives, and end up not being registers. 
llvm-svn: 35320
 2007-03-25 02:01:03 +00:00
Chris Lattner
104e73382c enforce the proper range for the i386 N constraint. 
llvm-svn: 35319
 2007-03-25 01:57:35 +00:00
Chris Lattner
92e2ee7b2d Fix test/CodeGen/X86/2007-03-24-InlineAsmPModifier.ll 
llvm-svn: 35318
 2007-03-25 01:44:57 +00:00
Anton Korobeynikov
63bff8af0c Autodetect MMX & SSE stuff for AMD processors 
llvm-svn: 35292
 2007-03-23 23:46:48 +00:00
Bill Wendling
124f2c8706 PR1260: 
Add final support to get the QT example to compile.

llvm-svn: 35290
 2007-03-23 22:35:46 +00:00
Bill Wendling
e6a9c6dfe6 We generate a shufflevector instruction, so we don't need the builtin 
intrinsic.

llvm-svn: 35269
 2007-03-22 20:29:26 +00:00
Bill Wendling
1bcad4c1cd Support added for shifts and unpacking MMX instructions. 
llvm-svn: 35266
 2007-03-22 18:42:45 +00:00
Dale Johannesen
44c0a5d545 repair x86 performance, dejagnu problems from previous change 
llvm-svn: 35245
 2007-03-21 21:51:52 +00:00
Dale Johannesen
fb7b59f5dd add generation of unnecessary push/pop around calls 
llvm-svn: 35241
 2007-03-21 21:16:39 +00:00
Evan Cheng
00a5cbf9e7 Mark re-materializable instructions. 
llvm-svn: 35230
 2007-03-21 00:16:56 +00:00
Evan Cheng
41f4f032ee Added MRegisterInfo hook to re-materialize an instruction. 
llvm-svn: 35205
 2007-03-20 08:09:38 +00:00
Chris Lattner
b9cc0ade43 Two changes: 
1) codegen a shift of a register as a shift, not an LEA.
2) teach the RA to convert a shift to an LEA instruction if it wants something
   in three-address form.

This gives us asm diffs like:

-       leal (,%eax,4), %eax
+       shll $2, %eax

which is faster on some processors and smaller on all of them.

and, more interestingly:

-       movl 24(%esi), %eax
-       leal (,%eax,4), %edi
+       movl 24(%esi), %edi
+       shll $2, %edi

Without #2, #1 was a significant pessimization in some cases.

This implements CodeGen/X86/shift-codegen.ll

llvm-svn: 35204
 2007-03-20 06:08:29 +00:00
Chris Lattner
59fe2be1c4 fix a warning 
llvm-svn: 35152
 2007-03-19 00:39:32 +00:00
Devang Patel
2dabb16eac Support 'I' inline asm constraint. 
llvm-svn: 35129
 2007-03-17 00:13:28 +00:00
Bill Wendling
8ced23ee5a And now support for MMX logical operations. 
llvm-svn: 35125
 2007-03-16 09:44:46 +00:00
Bill Wendling
feaff80149 Multiplication support for MMX. 
llvm-svn: 35118
 2007-03-15 21:24:36 +00:00
Evan Cheng
00edaa08b5 Under X86-64 large code model, do not emit 32-bit pc relative calls. 
llvm-svn: 35108
 2007-03-14 22:11:11 +00:00
Evan Cheng
fc80b5b712 Notes about codegen issues. 
llvm-svn: 35107
 2007-03-14 21:03:53 +00:00
Evan Cheng
50a0af3b57 Clean up. 
llvm-svn: 35105
 2007-03-14 20:20:19 +00:00
Evan Cheng
2617c8dd3a Oops. 
llvm-svn: 35104
 2007-03-14 19:44:58 +00:00
Evan Cheng
371b8e8fa9 X86-64 JIT is in large code model. Need stubs for direct calls. 
llvm-svn: 35097
 2007-03-14 10:51:55 +00:00
Evan Cheng
1092e481ce x86-64 JIT stub codegen. 
llvm-svn: 35096
 2007-03-14 10:48:08 +00:00
Evan Cheng
15de6714a4 Preliminary support for X86-64 JIT stub codegen. 
llvm-svn: 35095
 2007-03-14 10:44:30 +00:00
Evan Cheng
0eeb8b59eb More flexible TargetLowering LSR hooks for testing whether an immediate is 
a legal target address immediate or scale.

llvm-svn: 35073
 2007-03-12 23:28:50 +00:00
Evan Cheng
4224fa3617 Stupid bug: SSE2 supports v2i64 add / sub. 
llvm-svn: 35070
 2007-03-12 22:58:52 +00:00
Bill Wendling
236cfc4344 Adding more arithmetic operators to MMX. This is an almost exact copy of 
the addition. Please let me know if you have suggestions.

llvm-svn: 35055
 2007-03-10 09:57:05 +00:00
Bill Wendling
5fef3fd7e7 Added "padd*" support for MMX. Added MMX move stuff to X86InstrInfo so that 
moves, loads, etc. are recognized.

llvm-svn: 35031
 2007-03-08 22:09:11 +00:00
Evan Cheng
7d528d089c Putting more constants which do not contain relocations into .literal{4|8|16} 
llvm-svn: 35026
 2007-03-08 08:31:54 +00:00
Evan Cheng
14b63d89c1 Put constant data to .const, .const_data, .literal{4|8|16} sections. 
llvm-svn: 35016
 2007-03-08 01:07:07 +00:00
Bill Wendling
8f49ba1000 Remove useless pattern fragments. 
llvm-svn: 35009
 2007-03-07 18:23:09 +00:00
Anton Korobeynikov
85d6c1ebad Refactoring of formal parameter flags. Enable properly use of 
zext/sext/aext stuff.

llvm-svn: 35008
 2007-03-07 16:25:09 +00:00
Bill Wendling
3c201ddd02 Properly support v8i8 and v4i16 types. It now converts them to v2i32 for 
load and stores.

llvm-svn: 35002
 2007-03-07 05:43:18 +00:00
Anton Korobeynikov
090c2d50ea Fix DWARF debugging information on x86/Linux and (hopefully) 
Mingw32/Cygwin targets. This fixes PR978

llvm-svn: 35000
 2007-03-07 02:47:57 +00:00
Bill Wendling
a02d43fbbd Add LOAD/STORE support for MMX. 
llvm-svn: 34978
 2007-03-06 18:53:42 +00:00
Anton Korobeynikov
6da6c8c48b Use new SDIselParamAttr enumeration. This removes "magick" constants 
from formal attributes' flags processing.

llvm-svn: 34963
 2007-03-06 08:12:33 +00:00
Bill Wendling
c52174dee3 Add the emms intrinsic for MMX support. 
llvm-svn: 34938
 2007-03-05 23:09:45 +00:00
Chris Lattner
6d7701714e add missing braces 
llvm-svn: 34905
 2007-03-04 06:13:52 +00:00
Evan Cheng
2fb461c1b5 X86-64 VACOPY needs custom expansion. va_list is a struct { i32, i32, i8*, i8* }. 
llvm-svn: 34857
 2007-03-02 23:16:35 +00:00
Anton Korobeynikov
7cec92bcd2 Simplify things 
llvm-svn: 34849
 2007-03-02 21:50:27 +00:00
Chris Lattner
55dcf58453 argument lowering should copy from the vreg shadows of live-in arguments 
passed in registers, not directly from the pregs themselves.

llvm-svn: 34838
 2007-03-02 05:12:29 +00:00
Chris Lattner
e29ef5d9cb add a note 
llvm-svn: 34837
 2007-03-02 05:04:52 +00:00
Anton Korobeynikov
eaf27d276a Ensure that fastcall'ed function is correctly mangled & stack is 
properly aligned

llvm-svn: 34788
 2007-03-01 16:29:22 +00:00
Chris Lattner
bcc44762bc remove dead option 
llvm-svn: 34754
 2007-02-28 18:39:53 +00:00