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Commit Graph

214729 Commits

Author SHA1 Message Date
Tim Renouf
10b4ff5e22 [AMDGPU][llvm-objdump] Add lit.local.cfg missing from recent commit
Stops llvm-objdump tests failing when AMDGPU target is not supported.

Change-Id: Ic4ae443958c41c303ff6bee0966e5f21ab7a1851
2021-04-26 14:07:04 +01:00
Tim Renouf
79e5f97ca7 [MC][AMDGPU][llvm-objdump] Synthesized local labels in disassembly
1. Add an accessor function to MCSymbolizer to retrieve addresses
   referenced by a symbolizable operand, but not resolved to a symbol.
   That way, the caller can synthesize labels at those addresses and
   then retry disassembling the section.

2. Implement that in AMDGPU -- a failed symbol lookup results in the
   address being added to a vector returned by the new function.

3. Use that in llvm-objdump when using MCSymbolizer (which only happens
   on AMDGPU) and SymbolizeOperands is on.

Differential Revision: https://reviews.llvm.org/D101145

Change-Id: I19087c3bbfece64bad5a56ee88bcc9110d83989e
2021-04-26 13:56:36 +01:00
Sanjay Patel
08212f917c [IndVars] avoid 'tmp' names in test file with auto-generated CHECK lines; NFC
The script warns that this could be buggy when updating.
2021-04-26 08:32:25 -04:00
Yuanbo Li
5b6b066173 [LSR][DebugInfo] Don't unnecessarily drop DebugLocs
When transforming a loop terminating condition into a "max" comparison,
the DebugLoc from the old condition should be set on the newly created
comparison. They are the same operation, just optimized. Fixes PR48067.

Differential Revision: https://reviews.llvm.org/D98218
2021-04-26 13:14:42 +01:00
Bradley Smith
385ac4b46b [AArch64][SVE] Add missing patterns for scalar versions of SQSHL/UQSHL
Differential Revision: https://reviews.llvm.org/D101058
2021-04-26 13:07:12 +01:00
Dávid Bolvanský
ae044bb842 [InstCombine] Added testcases for PR50104, NFC 2021-04-26 14:00:30 +02:00
David Green
746a7315fd [ARM] Expand VMOVRRD simplification pattern
This expands the VMOVRRD(extract(..(build_vector(a, b, c, d)))) pattern,
to also handle insert_vectors. Providing we can find the correct insert,
this helps further simplify patterns by removing the redundant VMOVRRD.

Differential Revision: https://reviews.llvm.org/D100245
2021-04-26 12:27:38 +01:00
David Green
bd921d06d1 [ARM] Additional soft float BE test. NFC 2021-04-26 11:44:10 +01:00
David Sherwood
11992c16ee [NFC] Add scalable vectorisation tests for int/FP <> int/FP conversions
We can already vectorize loops that involve int<>int, fp<>fp, int<>fp
and fp<>int conversions, however we didn't previously have any tests
for them. This patch adds some tests for each conversion type.

Differential Revision: https://reviews.llvm.org/D99951
2021-04-26 11:01:14 +01:00
David Sherwood
6475ab5a00 [AArch64] Add AArch64TTIImpl::getMaskedMemoryOpCost function
When vectorising for AArch64 targets if you specify the SVE attribute
we automatically then treat masked loads and stores as legal. Also,
since we have no cost model for masked memory ops we believe it's
cheap to use the masked load/store intrinsics even for fixed width
vectors. This can lead to poor code quality as the intrinsics will
currently be scalarised in the backend. This patch adds a basic
cost model that marks fixed-width masked memory ops as significantly
more expensive than for scalable vectors.

Tests for the cost model are added here:

  Transforms/LoopVectorize/AArch64/masked-op-cost.ll

Differential Revision: https://reviews.llvm.org/D100745
2021-04-26 11:00:03 +01:00
Florian Hahn
cc6f98f11f [VPlan] Make blocksOnly work properly with ranges over const pointers.
When iterating over const blocks, the base type in the lambdas needs
to use const VPBlockBase *, otherwise it cannot be used with input
iterators over const VPBlockBase.

Also adjust the type of the input iterator range to const &, as it
does not take ownership of the input range.
2021-04-26 10:52:35 +01:00
David Green
df2cb039cf [ARM] Ensure loop invariant active.lane.mask operands
CGP can move instructions like a ptrtoint into a loop, but the
MVETailPredication when converting them will currently assume invariant
trip counts. This tries to ensure the operands are loop invariant, and
bails if not.

Differential Revision: https://reviews.llvm.org/D100550
2021-04-26 10:04:33 +01:00
Djordje Todorovic
2c383618e2 [llvm-dwarfdump] Fix split-dwarf bug in stats for inlined var loc cov
Initial (D96045) patch didn't handle split dwarf cases,
so this fixes that bug.

In addition, before applying this patch, we had a slowdown
that happened after the D96045. With this patch,
the slowdown will be fixed as well.

Differential Revision: https://reviews.llvm.org/D100951
2021-04-26 01:56:15 -07:00
Craig Topper
8aee2a9ea4 [RISCV] Cleanup setOperationAction calls for INTRINSIC_WO_CHAIN/INTRINSIC_W_CHAIN
We have several extensions that need i32 to be Custom for
INTRINSIC_WO_CHAIN with RV64 so enable it for all RV64.

For V extension, make i32 Custom for RV64 and i64 Custom for RV32.
When the i32 or i64 is legal, the operation action doesn't matter.
LegalizeDAG checks MVT::Other rather than the real type.
2021-04-25 23:44:28 -07:00
Ben Shi
d474a426e5 [RISCV] Optimize addition with immediate
Reviewed by: craig.topper

Differential Revision: https://reviews.llvm.org/D101244
2021-04-26 13:26:17 +08:00
Craig Topper
88feba99f6 [RISCV] Teach DAG combine what bits Zbp instructions demanded from their inputs.
This teaches DAG combine that shift amount operands for grev, gorc
shfl, unshfl only read a few bits.

This also teaches DAG combine that grevw, gorcw, shflw, unshflw,
bcompressw, bdecompressw only consume the lower 32 bits of their
inputs.

In the future we can teach SimplifyDemandedBits to also propagate
demanded bits of the output to the inputs in some cases.
2021-04-25 21:54:06 -07:00
Levy Hsu
b3953bd33d [RISCV] [1/2] Add IR intrinsic for Zbe extension
RV32/64:
bcompress
bdecompress

RV64 ONLY:
bcompressw
bdecompressw

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D101143
2021-04-25 19:14:34 -07:00
Jinsong Ji
7f7325057a [DebugInfo][AIX] Set target debugger-tune default to dbx
https://reviews.llvm.org/D99400 set clang DefaultDebuggerTuning for AIX
to dbx. However, we still need to update the target default so that llc
and other tools will get the same default debuggertuning, and avoid
passing extra options in LTO.

Reviewed By: #powerpc, shchenz, dblaikie

Differential Revision: https://reviews.llvm.org/D101197
2021-04-26 01:38:44 +00:00
Lang Hames
40970f078f [ORC] Avoid invalidating iterators in EHFrameRegistrationPlugin.
In EHFrameRegistrationPlugin::notifyTransferringResources if SrcKey had
eh-frames associated but DstKey did not we would create a new entry for DskKey,
invalidating the iterator for SrcKey in the process. This commit fixes that by
removing SrcKey first in this case.
2021-04-25 16:55:19 -07:00
Vitaly Buka
56f698ad6a [sanitizer] Use COMPILER_RT_EMULATOR with gtests
Reviewed By: morehouse

Differential Revision: https://reviews.llvm.org/D100998
2021-04-25 15:41:13 -07:00
Roman Lebedev
35f6937f2b [NFC][X86][AVX2] Add baseline CodeGen/CostModel tests for interleaved loads/stores of i16 w/ strides 2/3/4
`X86TTIImpl::getInterleavedMemoryOpCostAVX2()` currently contains data
only for a handful of tuples. For now, at least add tests for a few more.

I'm guessing that we care how well the patterns codegen since
we use their presumed cost for vectorization decisions,
so i've added codegen tests too.

There's one really easy caveat for these codegen tests:
for interleaved load tests, we really have to ensure that the
deinterleaved vectors are escaped separately. Similarly for stores.
2021-04-26 01:13:07 +03:00
Martin Storsjö
d49d24ce2d [googlemock] Fix warnings about superfluous semicolons after 68ff493dfc950c05c102e09e14a16d06253ffa16. NFC. 2021-04-25 23:41:37 +03:00
Nemanja Ivanovic
7653f36263 Disable deprecated-copy warnings on various LLVM code to bring the bot back to green
Bootstrap with `-Werror` is currently broken due to D79714.
This patch is required to bring the bootstrap bot back to green. The
code will likely need to be fixed and the pragmas removed in due time,
but for now we need to bring the bot back up.

Bot that is currently failing:
https://lab.llvm.org/buildbot/#/builders/36/builds/7680

Differential Revision: https://reviews.llvm.org/D101214
2021-04-25 12:41:46 -07:00
Vitaly Buka
6ad099fd48 [NFC] Fixed some D79714 warnings 2021-04-25 12:41:46 -07:00
Min-Yih Hsu
16f58ba2dc [ARM][disassembler] Fix incorrect number of MCOperands generated by the disassembler
Try to fix bug 49974.

This patch fixes two issues:

 1. BL does not use predicate (BL_pred is the predicate version of BL),
    so we shouldn't add predicate operands in DecodeBranchImmInstruction.
 2. Inside DecodeT2AddSubSPImm, we shouldn't add predicate operands into
    the MCInst because ARMDisassembler::AddThumbPredicate will do that for us.
    However, we should handle CC-out operand for t2SUBspImm and t2AddspImm.

Differential Revision: https://reviews.llvm.org/D100585
2021-04-25 11:55:10 -07:00
Florian Hahn
55f97d3d98 [VPlan] Add VPBlockUtils::blocksOnly helper.
This patch adds a blocksOnly helpers which take an iterator range
over VPBlockBase * or const VPBlockBase * and returns an interator
range that only include BlockTy blocks. The accesses are casted to
BlockTy.

Reviewed By: a.elovikov

Differential Revision: https://reviews.llvm.org/D101093
2021-04-25 17:38:09 +01:00
LLVM GN Syncbot
cc0eecb859 [gn build] Port 1cea7ab4ba13 2021-04-25 12:00:31 +00:00
Tomasz Miąsko
d94bcd2889 [demangler] Use standard semantics for StringView::substr
The StringView::substr now accepts a substring starting position and its
length instead of previous non-standard `from` & `to` positions.

All uses of two argument StringView::substr are in MicrosoftDemangler
and have 0 as a starting position, so no changes are necessary.

This also fixes a bug where attempting to extract a suffix with substr
(a `to` position equal to size) would return a substring without the
last character.

Fixing the issue should not introduce observable changes in the
demangler, since as currently used, a second argument to
StringView::substr is either: 1) a result of a successful call to
StringView::find and so necessarily smaller than size., or 2) in the
case of Demangler::demangleCharLiteral potentially equal to size, but
with demangler expecting more data to follow later on and failing either
way.

Reviewed By: #libc_abi, ldionne, erik.pilkington

Differential Revision: https://reviews.llvm.org/D100246
2021-04-25 13:56:41 +02:00
Simon Pilgrim
622199a58f Revert rG2149aa73f640c96 "[X86] Add support for reusing ZF etc. from locked XADD instructions (PR20841)"
This might be the cause of some msan build failures - I don't have access to a msan build right now, so this is a speculative revert.
2021-04-25 12:45:07 +01:00
LLVM GN Syncbot
1189a5806e [gn build] Port a354fd56c504 2021-04-25 11:27:54 +00:00
Simon Pilgrim
b2f9c3dec2 [X86] Add support for reusing ZF etc. from locked XADD instructions (PR20841)
XADD has the same EFLAGS behaviour as ADD
2021-04-25 12:02:33 +01:00
Simon Pilgrim
b90d4aa510 [X86] Add PR20841 test cases showing failure to reuse ZF from XADD ops 2021-04-25 11:50:18 +01:00
Simon Pilgrim
b5d73cafc6 [X86] Regenerate atomic-flags.ll test file 2021-04-25 11:50:18 +01:00
Florian Hahn
b7e8ac7d19 [NewGVN] Properly transfer PredDep in move constructor. 2021-04-25 11:22:59 +01:00
Florian Hahn
1f7961e68e [NewGVN] Use ExprResult to add extra predicate users.
This patch updates performSymbolicPredicateInfoEvaluation to manage
registering additional dependencies using ExprResult. Similar to D99987,
this fixes an issues where we failed to track the correct dependency for
a phi-of-ops value, which is marked as temporary.

Fixes PR49873.

Reviewed By: asbirlea, ruiling

Differential Revision: https://reviews.llvm.org/D100560
2021-04-25 11:13:32 +01:00
Simon Pilgrim
306d688bc4 [PhaseOrdering] Add PR32544 test coverage 2021-04-25 11:05:32 +01:00
Xiang1 Zhang
cf25c4dbf6 [X86] Refine AMX fast register allocation 2021-04-25 14:20:53 +08:00
Xiang1 Zhang
6da00a5d84 [X86] Support AMX fast register allocation
Differential Revision: https://reviews.llvm.org/D100026
2021-04-25 09:45:41 +08:00
Lang Hames
8daeb57ed9 [ORC][C-bindings] Fix missing ')' in comments. 2021-04-24 18:04:57 -07:00
Nikita Popov
de1f20abe1 [SCEV] Fix applyLoopGuards() chaining for ne predicates
ICMP_NE predicates directly overwrote the rewritten result,
instead of chaining it with previous rewrites, as was done for
ICMP_ULT and ICMP_ULE. This means that some guards were effectively
discarded, depending on their order.
2021-04-24 21:43:46 +02:00
Nikita Popov
bdb95d235c [SCEV] Add additional NE applyLoopGuards() test (NFC)
This is the same as @test_guard_ult_ne, just with the order of
the conditions swapped.
2021-04-24 21:36:23 +02:00
Nikita Popov
da6fbe8578 [PatternMatch] Improve m_Deferred() documentation (NFC)
m_Deferred() has nothing to do with commutative matchers, it needs
to be used whenever the value to match is determinde as part of
the same match expression.
2021-04-24 21:00:24 +02:00
RamNalamothu
065e9bee9e [NFC] Refactor how CFI section types are represented in AsmPrinter
In terms of readability, the `enum CFIMoveType` didn't better document what it
intends to convey i.e. the type of CFI section that gets emitted.

Reviewed By: dblaikie, MaskRay

Differential Revision: https://reviews.llvm.org/D76519
2021-04-24 23:29:42 +05:30
Dávid Bolvanský
7c4c0f3460 [Analysis] Attribute alignment should not prevent tail call optimization
Fixes tail folding issue mentioned in D100879.
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D101230
2021-04-24 19:57:42 +02:00
Florian Hahn
2aa8af916f [NewGVN] Use performSymbolicEvaluation instead of createExpression.
performSymbolicEvaluation is used to obtain the symbolic expression when
visiting instructions and this is used to determine their congruence
class.

performSymbolicEvaluation only creates expressions for certain
instructions (via createExpression). For unsupported instructions,
'unknown' expression are created.

The use of createExpression in processOutgoingEdges means we may
simplify the condition in processOutgoingEdges to a constant in the
initial round of processing, but we use Unknown(I) for the congruence
class. If an operand of I changes the expression Unknown(I) stays the
same, so there is no update of the congruence class of I. Hence it
won't get re-visited. So if an operand of I changes in a way that causes
createExpression to return different result, this update is missed.

This patch updates the code to use performSymbolicEvaluation, to be
symmetric with the congruence class updating code.

Reviewed By: asbirlea

Differential Revision: https://reviews.llvm.org/D99990
2021-04-24 18:49:07 +01:00
Dávid Bolvanský
abe87e4bc2 [InstCombine] Fixed UB in foldCtpop 2021-04-24 19:44:16 +02:00
David Green
1503461e4f [AArch64] Enable UseAA globally in the AArch64 backend
This is similar to D69796 from the ARM backend. We remove the UseAA
feature, enabling it globally in the AArch64 backend. This should in
general be an improvement allowing the backend to reorder more
instructions in scheduling and codegen, and enabling it by default helps
to improve the testing of the feature, not making it cpu-specific. A
debugging option is added instead for testing.

Differential Revision: https://reviews.llvm.org/D98781
2021-04-24 17:51:50 +01:00
Dávid Bolvanský
bf946c90e9 [Tests] Rename variable to fix broken buildbots 2021-04-24 18:45:50 +02:00
Dávid Bolvanský
3884c3dc13 [InstCombine] ctpop(rot(X)) -> ctpop(X)
Proof:
https://alive2.llvm.org/ce/z/ss2zyt - rotl
https://alive2.llvm.org/ce/z/ZM7Aue - rotr

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D101235
2021-04-24 18:25:03 +02:00
Dávid Bolvanský
e156538759 [InstCombine] ctpop(X) + ctpop(Y) => ctpop(X | Y) if X and Y have no common bits (PR48999)
For example:

```
int src(unsigned int a, unsigned int b)
{
    return __builtin_popcount(a << 16) + __builtin_popcount(b >> 16);
}

int tgt(unsigned int a, unsigned int b)
{
    return __builtin_popcount((a << 16)  | (b >> 16));
}
```

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D101210
2021-04-24 17:52:10 +02:00