Craig Topper
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3cb62dca0f
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Add X86 SARX, SHRX, and SHLX instructions.
llvm-svn: 142779
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2011-10-23 22:18:24 +00:00 |
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Craig Topper
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0e63b4485c
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Add X86 RORX instruction
llvm-svn: 142741
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2011-10-23 07:34:00 +00:00 |
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Craig Topper
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b1fa647871
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Rename PEXTR to PEXT. Add intrinsics for BMI instructions.
llvm-svn: 142480
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2011-10-19 07:48:35 +00:00 |
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Craig Topper
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6c900d9810
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Add X86 PEXTR and PDEP instructions.
llvm-svn: 142141
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2011-10-16 16:50:08 +00:00 |
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Craig Topper
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2cd868184c
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Add X86 BZHI instruction as well as BMI2 feature detection.
llvm-svn: 142122
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2011-10-16 07:55:05 +00:00 |
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Craig Topper
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4c6357d4af
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Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen
llvm-svn: 142105
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2011-10-16 03:51:13 +00:00 |
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Craig Topper
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62e63d9bb9
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Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.
llvm-svn: 142082
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2011-10-15 20:46:47 +00:00 |
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