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3597 Commits

Author SHA1 Message Date
Chris Lattner
087a1aaaab generalize aggregate handling 
llvm-svn: 36568
 2007-04-29 18:58:03 +00:00
Anton Korobeynikov
cb2004f82c Implement review feedback 
llvm-svn: 36564
 2007-04-29 18:02:48 +00:00
Chris Lattner
85e1cac6b7 memory operands that have a direct operand should have their stores created 
before the copies into physregs are done.  This avoids having flag operands
skip the store, causing cycles in the dag at sched time.  This fixes infinite
loops on these tests:

test/CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll for PR1308
test/CodeGen/PowerPC/2007-01-29-lbrx-asm.ll
test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll
test/CodeGen/X86/2006-07-12-InlineAsmQConstraint.ll for PR828

llvm-svn: 36547
 2007-04-28 21:12:06 +00:00
Chris Lattner
97d396d928 eliminate more redundant constraint type analysis 
llvm-svn: 36546
 2007-04-28 21:03:16 +00:00
Chris Lattner
4153538017 merge constraint type analysis stuff together. 
llvm-svn: 36545
 2007-04-28 21:01:43 +00:00
Chris Lattner
0e0d379b5d Significant refactoring of the inline asm stuff, to support future changes. 
No functionality change.

llvm-svn: 36544
 2007-04-28 20:49:53 +00:00
Anton Korobeynikov
45162c6dad Implement review feedback. Aliasees can be either GlobalValue's or 
bitcasts of them.

llvm-svn: 36537
 2007-04-28 13:45:00 +00:00
Chris Lattner
4c7178e326 memory inputs to an inline asm are required to have an address available. 
If the operand is not already an indirect operand, spill it to a constant
pool entry or a stack slot.

This fixes PR1356 and CodeGen/X86/2007-04-27-InlineAsm-IntMemInput.ll

llvm-svn: 36536
 2007-04-28 06:42:38 +00:00
Chris Lattner
0e2a4a7890 Fix CodeGen/Generic/2007-04-27-LargeMemObject.ll and 
CodeGen/Generic/2007-04-27-InlineAsm-X-Dest.ll

llvm-svn: 36534
 2007-04-28 06:08:13 +00:00
Chris Lattner
0a0983b493 Fix this to match change to InlineAsm class. 
llvm-svn: 36524
 2007-04-28 04:05:59 +00:00
Chris Lattner
51c23d862d Fix incorrect legalization of EHSELECTOR. This fixes 
CodeGen/Generic/2007-04-14-EHSelectorCrash.ll and PR1326

llvm-svn: 36510
 2007-04-27 17:12:52 +00:00
Evan Cheng
96a4c5fb05 Expand UINT_TO_FP in turns of SINT_TO_FP when UINTTOFP_* libcalls are not available. 
llvm-svn: 36501
 2007-04-27 07:33:31 +00:00
Chris Lattner
eef11c75d4 improve EH global handling, patch by Duncan Sands. 
llvm-svn: 36499
 2007-04-27 01:20:11 +00:00
Chris Lattner
92bff16acb enable Anton's shift/and switch lowering stuff! It now passes ppc bootstrap 
successfully! woohoo...

llvm-svn: 36496
 2007-04-26 21:09:43 +00:00
Anton Korobeynikov
3e0f9076d0 Fixx off-by-one bug, which prevents llvm-gcc bootstrap on ppc32 
llvm-svn: 36490
 2007-04-26 20:44:04 +00:00
Dan Gohman
bda4470e76 Fix a typo in a comment. 
llvm-svn: 36485
 2007-04-26 19:40:56 +00:00
Evan Cheng
eff332e3e1 Rename findRegisterUseOperand to findRegisterUseOperandIdx to avoid confusion. 
llvm-svn: 36483
 2007-04-26 19:00:32 +00:00
Evan Cheng
22fb2aa782 Minor bug. 
llvm-svn: 36473
 2007-04-26 08:24:22 +00:00
Evan Cheng
cfa2a787f7 Be careful when to add implicit kill / dead operands. Don't add them during / post reg-allocation. 
llvm-svn: 36458
 2007-04-26 01:40:09 +00:00
Evan Cheng
7f44e880dc Match MachineFunction::UsedPhysRegs changes. 
llvm-svn: 36452
 2007-04-25 22:13:27 +00:00
Evan Cheng
132ea465a1 Change UsedPhysRegs from array bool to BitVector to save some space. Setting / getting its states now go through MachineFunction. 
llvm-svn: 36451
 2007-04-25 22:10:09 +00:00
Evan Cheng
c3b686ff44 Clean up. 
llvm-svn: 36449
 2007-04-25 21:34:08 +00:00
Evan Cheng
e464e596a6 Data structure change to improve compile time (especially in debug mode). 
llvm-svn: 36447
 2007-04-25 19:34:00 +00:00
Evan Cheng
c713a5ea36 This was lefted out. Fixed sumarray-dbl. 
llvm-svn: 36445
 2007-04-25 18:33:21 +00:00
Anton Korobeynikov
25dc9a61cb Implement aliases. This fixes PR1017 and it's dependent bugs. CFE part 
will follow.

llvm-svn: 36435
 2007-04-25 14:27:10 +00:00
Evan Cheng
e884f9cb2a Fix for PR1306. 
- A register def / use now implicitly affects sub-register liveness but does
not affect liveness information of super-registers.
- Def of a larger register (if followed by a use later) is treated as
read/mod/write of a smaller register.

llvm-svn: 36434
 2007-04-25 07:30:23 +00:00
Evan Cheng
4f48ec6738 Clean up. 
llvm-svn: 36431
 2007-04-25 07:18:20 +00:00
Chris Lattner
ca7480e8cb support for >4G stack frames 
llvm-svn: 36425
 2007-04-25 04:30:24 +00:00
Chris Lattner
a2b590fff8 support > 4G stack objects 
llvm-svn: 36422
 2007-04-25 04:20:54 +00:00
Chris Lattner
8860742825 allow support for 64-bit stack objects 
llvm-svn: 36420
 2007-04-25 04:08:28 +00:00
Chris Lattner
64bb6c0a08 Be more careful about folding op(x, undef) when we have vector operands. 
This fixes CodeGen/X86/2007-04-24-VectorCrash.ll

llvm-svn: 36413
 2007-04-25 00:00:45 +00:00
Bill Wendling
b3b0427654 Assertion when using a 1-element vector for an add operation. Get the 
real vector type in this case.

llvm-svn: 36402
 2007-04-24 21:13:23 +00:00
Scott Michel
5a33297ae3 Use '-1U' where '-1UL' is obvious overkill, eliminating gcc warnings about 
tests always being true in the process.

llvm-svn: 36387
 2007-04-24 01:24:20 +00:00
Dale Johannesen
c878c6c2ed modify per review commentary 
llvm-svn: 36383
 2007-04-23 23:33:31 +00:00
Dale Johannesen
0b2847d8c4 make EmitAlignment work the way Chris says it should 
llvm-svn: 36368
 2007-04-23 19:58:54 +00:00
Christopher Lamb
a157874a8a PR400 phase 2. Propagate attributed load/store information through DAGs. 
llvm-svn: 36356
 2007-04-22 23:15:30 +00:00
Lauro Ramos Venancio
3b60b9546e X86 TLS: Implement review feedback. 
llvm-svn: 36318
 2007-04-21 20:56:26 +00:00
Reid Spencer
81070d52da Revert Christopher Lamb's load/store alignment changes. 
llvm-svn: 36309
 2007-04-21 18:36:27 +00:00
Christopher Lamb
b56b6a7ad7 add support for alignment attributes on load/store instructions 
llvm-svn: 36301
 2007-04-21 08:16:25 +00:00
Lauro Ramos Venancio
a6bb7b3907 Allow the lowering of ISD::GLOBAL_OFFSET_TABLE. 
llvm-svn: 36290
 2007-04-20 23:02:39 +00:00
Lauro Ramos Venancio
bc32d90b46 Implement "general dynamic", "initial exec" and "local exec" TLS models for 
X86 32 bits.

llvm-svn: 36283
 2007-04-20 21:38:10 +00:00
Evan Cheng
fbbdb92c9d VarInfo::UsedBlocks is no longer used. Remove. 
llvm-svn: 36250
 2007-04-18 05:04:38 +00:00
Chris Lattner
ea3c945817 allow SRL to simplify its operands, as it doesn't demand all bits as input. 
llvm-svn: 36245
 2007-04-18 03:06:49 +00:00
Chris Lattner
4ce8602d58 When replacing a node in SimplifyDemandedBits, if the old node used any 
single-use nodes, they will be dead soon.  Make sure to remove them before
processing other nodes.  This implements CodeGen/X86/shl_elim.ll

llvm-svn: 36244
 2007-04-18 03:05:22 +00:00
Chris Lattner
639f807048 fix a pasto 
llvm-svn: 36242
 2007-04-18 03:01:40 +00:00
Evan Cheng
1325999a14 Don't populate TryAgainList when coalescing only physical registers with virtual registers. 
llvm-svn: 36240
 2007-04-18 02:30:19 +00:00
Evan Cheng
eecfac47a8 Increment use count of new virtuals created during PHI elimination. 
llvm-svn: 36233
 2007-04-18 00:36:11 +00:00
Chris Lattner
1677782ef0 Fix a bug in my previous patch, grabbing the shift amount width from the 
wrong operand.

llvm-svn: 36223
 2007-04-17 22:53:02 +00:00
Chris Lattner
b55496c660 Fold (x << c1)>> c2 into a single shift if the bits shifted out aren't used. 
This compiles:
int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }

into:
_baz:
        srwi r2, r3, 1
        extsh r3, r2
        blr

on PPC, instead of:
_baz:
        slwi r2, r3, 8
        srwi r2, r2, 9
        extsh r3, r2
        blr

GCC produces:
_baz:
        srwi r10,r4,24
        insrwi r10,r3,24,0
        srawi r9,r3,24
        srawi r3,r10,9
        extsh r3,r3
        blr

This implements CodeGen/PowerPC/shl_elim.ll

llvm-svn: 36221
 2007-04-17 21:14:16 +00:00
Evan Cheng
48352d7a71 Copy coalescing change to prevent a physical register from being pin to a 
long live interval that has low usage density.
1. Change order of coalescing to join physical registers with virtual
   registers first before virtual register intervals become too long.
2. Check size and usage density to determine if it's worthwhile to join.
3. If joining is aborted, assign virtual register live interval allocation
   preference field to the physical register.
4. Register allocator should try to allocate to the preferred register
   first (if available) to create identify moves that can be eliminated.

llvm-svn: 36218
 2007-04-17 20:32:26 +00:00