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Commit Graph

4234 Commits

Author SHA1 Message Date
Matthias Braun
9e9e0f5d4c Tests: Do not unnecessarily depend on kill comments
llvm-svn: 192404
2013-10-10 22:37:49 +00:00
Benjamin Kramer
11421cc493 Disable function padding to get this test to pass on atom.
llvm-svn: 192348
2013-10-10 12:46:23 +00:00
Elena Demikhovsky
f24ecf7862 AVX-512: Added VRCP28 and VRSQRT28 instructions and intrinsics.
llvm-svn: 192283
2013-10-09 08:16:14 +00:00
Craig Topper
d5082631e1 Add in64BitMode/in32BitMode to the MMX/SSE2/AVX maskmovq/dq instructions. This way the asm parser will pick the right one based on the mode. Instruction selection already did the right thing based on the pointer size.
llvm-svn: 192266
2013-10-09 02:18:34 +00:00
Craig Topper
2d70555027 Fix a typo in the mattr part of the run line.
llvm-svn: 192174
2013-10-08 06:12:26 +00:00
Craig Topper
3d7c6afb79 Explicitly disable AVX on a bunch of tests so they won't fail on AVX machines post r192171.
llvm-svn: 192173
2013-10-08 06:06:57 +00:00
Craig Topper
aa1a4d51f0 Remove some instructions that existed to provide aliases to the assembler. Can be done with InstAlias instead. Unfortunately, this was causing printer to use 'vmovq' or 'vmovd' based on what was parsed. To cleanup the inconsistencies convert all 'vmovd' with 64-bit registers to 'vmovq', but provide an alias so that 'vmovd' will still parse.
llvm-svn: 192171
2013-10-08 05:53:50 +00:00
Benjamin Kramer
feace9b737 X86: Fix type check. Just because an integer type is illegal doesn't mean it's i64.
Fixes PR17495, where an i24 triggered this code. It's intended to
optimize i64 loads on 32 bit x86.

llvm-svn: 192123
2013-10-07 19:11:35 +00:00
Matt Arsenault
9c8541d286 Change objectsize intrinsic to accept different address spaces.
Bitcasting everything to i8* won't work. Autoupgrade the old
intrinsic declarations to use the new mangling.

llvm-svn: 192117
2013-10-07 18:06:48 +00:00
Rafael Espindola
499aaf305a Add support for aliases with linkonce_odr.
This will be used to extend constructor aliases in clang.

llvm-svn: 192066
2013-10-06 15:10:43 +00:00
Benjamin Kramer
44710574cb Force a CPU that doesn't have AVX, otherwise this test fails.
llvm-svn: 192065
2013-10-06 13:52:41 +00:00
Benjamin Kramer
a7e734d765 X86: Don't fold spills into SSE operations if the stack is unaligned.
Regalloc can emit unaligned spills nowadays, but we can't fold the
spills into SSE ops if we can't guarantee alignment. PR12250.

llvm-svn: 192064
2013-10-06 13:48:22 +00:00
Elena Demikhovsky
cb8eaca2e4 AVX-512: added scalar convert instructions and intrinsics.
Fixed load folding in VPERM2I instruction.

llvm-svn: 192063
2013-10-06 13:11:09 +00:00
Elena Demikhovsky
0ff833ab99 AVX-512: fixed shuffle lowering
in case of BLEND and added VSHUFPS patterns.

llvm-svn: 192055
2013-10-06 06:11:18 +00:00
Benjamin Kramer
3a6afef4e7 Emit a better error when running out of registers on inline asm.
The most likely case where this error happens is when the user specifies
too many register operands. Don't make it look like an internal LLVM bug
when we can see that the error is coming from an inline asm instruction.
For other instructions we keep the "ran out of registers" error.

llvm-svn: 192041
2013-10-05 19:33:37 +00:00
Craig Topper
0a8f3fc996 Remove unneeded TBM intrinsics. The arithmetic/logical operation patterns are sufficient.
llvm-svn: 192039
2013-10-05 19:22:59 +00:00
Craig Topper
d0a63f6722 Add an additional pattern for BLCI since opt can turn (not (add x, 1)) into (sub -2, x).
llvm-svn: 192037
2013-10-05 17:17:53 +00:00
Rafael Espindola
86d473eceb Convert test to FileCheck.
llvm-svn: 192025
2013-10-05 02:58:36 +00:00
Craig Topper
5b62ea95ec Remove duplicated test cases that occurred when I applied the same patch file to my model twice.
llvm-svn: 191873
2013-10-03 04:27:14 +00:00
Craig Topper
5ac188d0f2 Add patterns for selecting TBM instructions from logical operations. Patch from Yunzhong Gao.
llvm-svn: 191871
2013-10-03 04:16:45 +00:00
Elena Demikhovsky
ee11e148e9 AVX-512: fixed a bug in getLoadStoreRegOpcode() for AVX-512 target
llvm-svn: 191818
2013-10-02 12:20:42 +00:00
Preston Gurd
c52dfda610 Add test case for PR16785.
Thanks for Dimitry Andric, Rafael Espindola, and Benjamin Kramer
for providing and progressively reducing the test case!

llvm-svn: 191782
2013-10-01 17:02:48 +00:00
Elena Demikhovsky
84c6cd222d AVX-512: Added X86vzmovl patterns
llvm-svn: 191733
2013-10-01 08:38:02 +00:00
Manman Ren
799fd39420 TBAA: remove !tbaa from testing cases when they are not needed.
llvm-svn: 191689
2013-09-30 18:17:35 +00:00
Yunzhong Gao
e51da27a74 Adding intrinsics to the llvm backend for TBM instruction set.
Phabricator code review is located here: http://llvm-reviews.chandlerc.com/D1750

llvm-svn: 191539
2013-09-27 18:38:42 +00:00
Andrea Di Biagio
a10165167b Remove superfluous comment accidentally checked-in.
llvm-svn: 191513
2013-09-27 12:13:58 +00:00
Andrea Di Biagio
a96ff5eeac Re-apply the change from r191393 with fix for pr17380.
This change fixes the problem reported in pr17380 and re-add the dagcombine 
transformation ensuring that the value types are always legal if the 
transformation is triggered after Legalization took place.

Added the test case from pr17380.

llvm-svn: 191509
2013-09-27 11:37:05 +00:00
Andrea Di Biagio
0901efb8fb Revert r191393 since it caused pr17380.
llvm-svn: 191438
2013-09-26 16:54:01 +00:00
Josh Magee
2c804b5636 Test commit. Removed trailing whitespace.
llvm-svn: 191402
2013-09-25 22:07:48 +00:00
Andrea Di Biagio
1968361975 Teach DAGCombiner how to canonicalize dags according to the rule
(shl (zext (shr A, X)), X) => (zext (shl (shr A, X), X)).

The rule only triggers when there are no other uses of the
zext to avoid materializing more instructions.

This helps the DAGCombiner understand that the shl/shr
sequence can then be converted into an and instruction.

llvm-svn: 191393
2013-09-25 19:01:01 +00:00
Eli Friedman
bdb3e2822e Add missing check to SETCC optimization.
PR17338.

llvm-svn: 191337
2013-09-24 22:50:14 +00:00
Michael Gottesman
a2ef7dd057 [stackprotector] Forgot to add in PR number to test case.
llvm-svn: 191261
2013-09-24 02:10:55 +00:00
Michael Gottesman
2ec63d27a9 [stackprotector] Allow for copies from vreg -> vreg to be in a terminator sequence.
Sometimes a copy from a vreg -> vreg sneaks into the middle of a terminator
sequence. It is safe to slice this into the stack protector success bb.

This fixes PR16979.

llvm-svn: 191260
2013-09-24 01:50:26 +00:00
Bill Wendling
339b0f39aa Selecting the address from a very long chain of GEPs can blow the stack.
The recursive nature of the address selection code can cause the stack to
explode if there is a long chain of GEPs. Convert the recursive bit into a
iterative method to avoid this.

<rdar://problem/12445434>

llvm-svn: 191252
2013-09-24 00:13:08 +00:00
Ben Langmuir
706a7ccbeb Add sha intrinsic tests
These should have been included with r190864, but I forgot to use svn add.

llvm-svn: 191208
2013-09-23 16:57:52 +00:00
Tim Northover
c9a7e47164 ISelDAG: spot chain cycles involving MachineNodes
Previously, the DAGISel function WalkChainUsers was spotting that it
had entered already-selected territory by whether a node was a
MachineNode (amongst other things). Since it's fairly common practice
to insert MachineNodes during ISelLowering, this was not the correct
check.

Looking around, it seems that other nodes get their NodeId set to -1
upon selection, so this makes sure the same thing happens to all
MachineNodes and uses that characteristic to determine whether we
should stop looking for a loop during selection.

This should fix PR15840.

llvm-svn: 191165
2013-09-22 08:21:56 +00:00
Juergen Ributzka
b55735e2d8 Revert "SelectionDAG: Teach the legalizer to split SETCC if VSELECT needs splitting too."
This reverts commit r191130.

llvm-svn: 191138
2013-09-21 15:09:46 +00:00
Juergen Ributzka
32cca125e1 [X86] Emulate AVX 256bit MIN/MAX support by splitting the vector.
In AVX 256bit vectors are valid vectors and therefore the Type Legalizer doesn't
split the VSELECT and SETCC nodes. AVX only supports MIN/MAX on 128bit vectors
and this fix enables vector splitting for this special case in the X86 DAG
Combiner.

This fix is related to PR16695, PR17002, and <rdar://problem/14594431>.

llvm-svn: 191131
2013-09-21 04:55:22 +00:00
Juergen Ributzka
67e5289ff2 SelectionDAG: Teach the legalizer to split SETCC if VSELECT needs splitting too.
The Type Legalizer recognizes that VSELECT needs to be split, because the type
is to wide for the given target. The same does not always apply to SETCC,
because less space is required to encode the result of a comparison. As a result
VSELECT is split and SETCC is unrolled into scalar comparisons.

This commit fixes the issue by checking for VSELECT-SETCC patterns in the DAG
Combiner. If a matching pattern is found, then the result mask of SETCC is
promoted to the expected vector mask for the given target. This mask has usually
te same size as the VSELECT return type (except for Intel KNL). Now the type
legalizer will split both VSELECT and SETCC.

This allows the following X86 DAG Combine code to sucessfully detect the MIN/MAX
pattern. This fixes PR16695, PR17002, and <rdar://problem/14594431>.

llvm-svn: 191130
2013-09-21 04:55:18 +00:00
Kai Nacke
64a3fccd60 PR16726: extend rol/ror matching
C-like languages promote types like unsigned short to unsigned int before
performing an arithmetic operation. Currently the rotate matcher in the
DAGCombiner does not consider this situation.

This commit extends the DAGCombiner in the way that the pattern

(or (shl ([az]ext x), (*ext y)), (srl ([az]ext x), (*ext (sub 32, y))))

is folded into

([az]ext (rotl x, y))

The matching is restricted to aext and zext because in this cases the upper
bits are either undefined or known. Test case is included.

This fixes PR16726.

llvm-svn: 191049
2013-09-19 23:00:28 +00:00
Kai Nacke
21c0476931 Revert PR16726: extend rol/ror matching
There is a buildbot failure. Need to investigate this.

llvm-svn: 191048
2013-09-19 22:53:36 +00:00
Kai Nacke
fe02753846 PR16726: extend rol/ror matching
C-like languages promote types like unsigned short to unsigned int before
performing an arithmetic operation. Currently the rotate matcher in the
DAGCombiner does not consider this situation.

This commit extends the DAGCombiner in the way that the pattern

(or (shl ([az]ext x), (*ext y)), (srl ([az]ext x), (*ext (sub 32, y))))

is folded into

([az]ext (rotl x, y))

The matching is restricted to aext and zext because in this cases the upper
bits are either undefined or known. Test case is included.

This fixes PR16726.

llvm-svn: 191045
2013-09-19 22:36:39 +00:00
Bill Wendling
01837a249d Add testcase to make sure we don't generate too many jumps for a une compare.
<rdar://problem/7859988>

llvm-svn: 191040
2013-09-19 21:58:20 +00:00
Benjamin Kramer
f939b2b330 DAGCombiner: Don't fold vector muls with constants that look like a splat of a power of 2 but differ in bit width.
PR17283.

llvm-svn: 191000
2013-09-19 13:28:20 +00:00
Tim Northover
89d57eb12b X86: FrameIndex addressing modes do have a base register.
When selecting the DAG (add (WrapperRIP ...), (FrameIndex ...)), X86 code had
spotted the FrameIndex possibility and was working out whether it could fold
the WrapperRIP into this.

The test for forming a %rip version is notionally whether we already have a
base or index register (%rip precludes both), but we were forgetting to account
for the register that would be inserted later to access the frame.

rdar://problem/15024520

llvm-svn: 190995
2013-09-19 11:33:53 +00:00
Preston Gurd
efaca57b70 Attempt to fix llvm-ppc64-linux2 buildbot failure by adding
-march=x86 to SLM test.

llvm-svn: 190958
2013-09-18 21:39:33 +00:00
Preston Gurd
1800994293 Verify that llvm can generate the prefetchw instruction when the CPU is
Atom Silvermont.

Patch by Sriram Murali.

llvm-svn: 190957
2013-09-18 21:08:09 +00:00
Craig Topper
5d022196de Lift alignment restrictions for load/store folding on VINSERTF128/VEXTRACTF128. Fixes PR17268.
llvm-svn: 190916
2013-09-18 03:55:53 +00:00
Reid Kleckner
130539949d COFF: Ensure that objects produced by LLVM link with /safeseh
Summary:
We indicate that the object files are safe by emitting a @feat.00
absolute address symbol.  The address is presumably interpreted as a
bitfield of features that the compiler would like to enable.  Bit 0 is
documented in the PE COFF spec to opt in to "registered SEH", which is
what /safeseh enables.

LLVM's object files are safe by default because LLVM doesn't know how to
produce SEH handlers.

Reviewers: Bigcheese

CC: llvm-commits

Differential Revision: http://llvm-reviews.chandlerc.com/D1691

llvm-svn: 190898
2013-09-17 23:18:05 +00:00
Preston Gurd
6efe5100eb Add Atom Silvermont (slm) tests
- check that -mcpu=slm uses the call register indirect optimization
- check that -mcpu=slm runs the scheduler 
- check that -mcpu=slm supports the movbe instruction

llvm-svn: 190814
2013-09-16 22:22:07 +00:00