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65 Commits

Author SHA1 Message Date
Daniel Sanders
d1189ed726 [mips][sched] Split IILogic into II_AND, II_OR, II_XOR, II_ANDI, II_ORI, II_XORI 
This is necessary because the classes are shared between all implementations.

No functional change since the InstrItinData's have been duplicated.

llvm-svn: 199394
 2014-01-16 15:57:05 +00:00
Daniel Sanders
b055d0c245 [mips][sched] Split IIArith in preparation for the first scheduler targeting a specific MIPS CPU. 
IIArith -> II_ADD, II_ADDU, II_AND, II_CL[ZO], II_DADDIU, II_DADDU,
  II_DROTR, II_DROTR32, II_DROTRV, II_DSLL, II_DSLL32, II_DSLLV,
  II_DSR[AL], II_DSR[AL]32, II_DSR[AL]V, II_DSUBU, II_LUI, II_MOV[ZFNT],
  II_NOR, II_OR, II_RDHWR, II_ROTR, II_ROTRV, II_SLL, II_SLLV, II_SR[AL],
  II_SR[AL]V, II_SUBU, II_XOR

No functional change since the InstrItinData's have been duplicated.

This is necessary because the classes are shared between all schedulers.

Once this patch series is committed there will be an InstrItinClass for
each mnemonic with minimal grouping. This does increase the size of the
itinerary tables for each MIPS scheduler but we have a few options for dealing
with that later. These options include reducing the number of classes once
we see the best way to simplify them, or by extending tablegen to be able
to compress the table by eliminating duplicates entries, etc.

llvm-svn: 199391
 2014-01-16 14:27:20 +00:00
Daniel Sanders
aa869714a0 [mips] IIImult should have an InstrItinData in the generic scheduler. Used the same one as for IIImul. 
Affects:
  DMULT, DMULTu, MADD, MADD_MM, MADDU, MADDU_MM, MSUB, MSUB_MM, MSUBU,
  MSUBU_MM, MULT, MULTu

Does not affect MULT_MM, MULTu_MM since they are currently miscategorised
as IIImul.

llvm-svn: 199381
 2014-01-16 13:45:53 +00:00
Akira Hatanaka
d0c19bc118 [mips] Define instruction itineraries IIArith and IILogic. 
No functionality change.

llvm-svn: 187468
 2013-07-31 00:55:34 +00:00
Akira Hatanaka
b94a7de0c8 [mips] Add instruction itinerary classes for mult, seb and slt instructions. 
llvm-svn: 186222
 2013-07-12 22:43:20 +00:00
Akira Hatanaka
1b1f481a6c [mips] Add new InstrItinClasses for move from/to coprocessor instructions and 
floating point loads and stores.

No changes in functionality.

llvm-svn: 185399
 2013-07-02 00:00:02 +00:00
Jia Liu
bdcd314be3 remove blanks, and some code format 
llvm-svn: 151625
 2012-02-28 07:46:26 +00:00
Akira Hatanaka
74d45b54f1 Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality. 
llvm-svn: 129612
 2011-04-15 21:51:11 +00:00
Akira Hatanaka
6f900185ed Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality. 
llvm-svn: 129606
 2011-04-15 21:00:26 +00:00
Bruno Cardoso Lopes
5400401372 Remove (hopefully) all trailing whitespaces from the mips backend. Patch by Hatanaka, Akira 
llvm-svn: 127003
 2011-03-04 17:51:39 +00:00
Evan Cheng
39c462b4f1 Add support to model pipeline bypass / forwarding. 
llvm-svn: 115005
 2010-09-28 23:50:49 +00:00
Chris Lattner
a556264e06 fix emacs language spec's, patch by Edmund Grimley-Evans! 
llvm-svn: 111241
 2010-08-17 16:20:04 +00:00
Anton Korobeynikov
e325c693a5 Make processor FUs unique for given itinerary. This extends the limit of 32 
FU per CPU arch to 32 per intinerary allowing precise modelling of quite
complex pipelines in the future.

llvm-svn: 101754
 2010-04-18 20:31:01 +00:00
Chris Lattner
ad9a6ccb83 Remove attribution from file headers, per discussion on llvmdev. 
llvm-svn: 45418
 2007-12-29 20:36:04 +00:00
Bruno Cardoso Lopes
d67580757e Mips generic fallback instruction schedule support! 
llvm-svn: 41149
 2007-08-18 01:46:44 +00:00