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Commit Graph

157286 Commits

Author SHA1 Message Date
Adam Nemet
2885645683 Add opt-viewer testing
Detects whether we have the Python modules (pygments, yaml) required by
opt-viewer and hooks this up to REQUIRES.

This fixes https://bugs.llvm.org/show_bug.cgi?id=34129 (the lack of opt-viewer
testing).

It's also related to https://github.com/apple/swift/pull/12938 and the idea is
to expose LLVM_HAVE_OPT_VIEWER_MODULES to the Swift cmake.

Differential Revision: https://reviews.llvm.org/D40202

Fixes since the first commit:
1. Disable syntax highlighting as different versions of pygments generate
different HTML
2. Use llvm-cxxfilt from the build

llvm-svn: 319324
2017-11-29 17:07:41 +00:00
Sander de Smalen
f54f612a70 Reverted r319315 because of unused functions (due to PPR not yet being
used by any instructions).

llvm-svn: 319321
2017-11-29 15:14:39 +00:00
Simon Pilgrim
97088da9e8 [X86][AVX512] Tag VPERMILV instruction scheduler class
llvm-svn: 319316
2017-11-29 14:58:34 +00:00
Sander de Smalen
a1e07e5345 [AArch64][SVE] Asm: Add SVE predicate register definitions and parsing support
Summary: Patch [1/4] in a series to add parsing of predicates and properly parse SVE ZIP1/ZIP2 instructions.

Reviewers: rengolin, kristof.beyls, fhahn, mcrosier, evandro, echristo, efriedma

Reviewed By: fhahn

Subscribers: aemerson, javed.absar, llvm-commits, tschuett

Differential Revision: https://reviews.llvm.org/D40360

llvm-svn: 319315
2017-11-29 14:34:18 +00:00
Diana Picus
ded22a182d [ARM GlobalISel] Fix selecting G_BRCOND
When lowering a G_BRCOND, we generate a TSTri of the condition against
1, which sets the flags, and then a Bcc which branches based on the
value of the flags.

Unfortunately, we were using the wrong condition code to check whether
we need to branch (EQ instead of NE), which caused all our branches to
do the opposite of what they were intended to do. This patch fixes the
issue by using the correct condition code.

llvm-svn: 319313
2017-11-29 14:20:06 +00:00
Simon Pilgrim
3df6922e61 [X86][AVX512] Setup unary (PABS/VPLZCNT/VPOPCNT/VPCONFLICT/VMOV*DUP) instruction scheduler classes
llvm-svn: 319312
2017-11-29 13:49:51 +00:00
Dmitry Preobrazhensky
d68c59f82f [AMDGPU][MC][GFX9] Corrected mapping of GFX9 v_add/sub/subrev_u32
When translating pseudo to MC, v_add/sub/subrev_u32 shall be mapped via a separate table as GFX8 has opcodes with the same names.
These instructions shall also be labelled as renamed for pseudoToMCOpcode to handle them correctly.

Reviewers: arsenm

Differential Revision: https://reviews.llvm.org/D40550

llvm-svn: 319311
2017-11-29 13:33:40 +00:00
Simon Pilgrim
5cb6eddd64 [X86][SSE] Merged sse2_unpack and sse2_unpack PUNPCK instruction templates. NFCI.
llvm-svn: 319310
2017-11-29 12:12:27 +00:00
Simon Pilgrim
776052e10a [X86][SSE] Merged sse2_pack and sse2_pack_y PACKSS/PACKUS instruction templates. NFCI.
llvm-svn: 319308
2017-11-29 11:35:45 +00:00
Max Kazantsev
211c129f74 [SCEV][NFC] Break from loop after we found first non-Phi in getAddRecExprPHILiterally
llvm-svn: 319306
2017-11-29 10:54:16 +00:00
Oliver Stannard
63bc6a6d13 [ARM] Add support for armv7e-m to the .arch directive
This will allow compilation of assembly files targeting armv7e-m without having
to specify the Tag_CPU_arch attribute as a workaround.

Differential revision: https://reviews.llvm.org/D40370

Patch by Ian Tessier!

llvm-svn: 319303
2017-11-29 10:12:15 +00:00
Serguei Katkov
eb151e837e [CGP] Enable complex addr mode
Enable complex addr modes after two critical fixes: rL319109 and rL319292

llvm-svn: 319302
2017-11-29 09:48:50 +00:00
Jonas Paulsson
339e0213f4 Comment fix in SelectionDAG.h
/// Replace any uses of From with To, leaving
-  /// uses of other values produced by From.Val alone.
+  /// uses of other values produced by From.getNode() alone.
   void ReplaceAllUsesOfValueWith(SDValue From, SDValue To);

(this is what it says in the .cpp file above this method)

llvm-svn: 319301
2017-11-29 09:16:37 +00:00
Craig Topper
bc2220af38 [X86] Remove setOperationAction Promote for ISD::SINT_TO_FP MVT::v8i16/v16i8/v16i16.
A DAG combine ensures these ops are always promoted to vXi32.

llvm-svn: 319298
2017-11-29 08:19:36 +00:00
Max Kazantsev
610c61986d [SCEV][NFC] Remove condition that can never happen due to check few lines above
llvm-svn: 319293
2017-11-29 06:10:36 +00:00
Serguei Katkov
3833a715be [CGP] Fix common type handling in optimizeMemoryInst
If common type is different we should bail out due to we will not be
able to create a select or Phi of these values.

Basically it is done in ExtAddrMode::compare however it does not work
if we handle the null first and then two values of different types.
so add a check in initializeMap as well. The check in ExtAddrMode::compare
is used as earlier bail out.

Reviewers: reames, john.brawn
Reviewed By: john.brawn
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D40479

llvm-svn: 319292
2017-11-29 05:51:26 +00:00
Sean Fertile
c5080e62bc [PowerPC] Relax the checking on AND/AND8 in isSignOrZeroExtended.
Separate the handling of AND/AND8 out from PHI/OR/ISEL checking. The reasoning
is the others need all their operands to be sign/zero extended for their output
to also be sign/zero extended. This is true for AND and sign-extension, but for
zero-extension we only need at least one of the input operands to be zero
extended for the result to also be zero extended.

Differential Revision: https://reviews.llvm.org/D39078

llvm-svn: 319289
2017-11-29 04:09:29 +00:00
Matt Arsenault
d1baa17c1b AMDGPU: Use stricter regexes for add instructions
Match the entire _co as one optional piece rather than
a set of characters to match multiple times.

llvm-svn: 319275
2017-11-29 02:25:14 +00:00
Bruno Cardoso Lopes
6ead7b4924 [Modules] Add textual headers for recently added .def files
Keep module.modulemap up to date and get rid of -Wincomplete-umbrella warnings

rdar://problem/35711925

llvm-svn: 319273
2017-11-29 01:53:49 +00:00
Matt Arsenault
1ba67865c4 DAG: Add nuw when splitting loads and stores
The object can't straddle the address space
wrap around, so I think it's OK to assume any
offsets added to the base object pointer can't
overflow. Similar logic already appears to be
applied in SelectionDAGBuilder when lowering
aggregate returns.

llvm-svn: 319272
2017-11-29 01:25:12 +00:00
Adrian Prantl
404a2c9dce llvm-dwarfdump: honor the --show-children option when dumping a specific DIE.
llvm-svn: 319271
2017-11-29 01:12:22 +00:00
Matt Arsenault
6fa14c4ed9 AMDGPU: Select DS insts without m0 initialization
GFX9 stopped using m0 for most DS instructions. Select
a different instruction without the use. I think this will
be less error prone than trying to manually maintain m0
uses as needed.

llvm-svn: 319270
2017-11-29 00:55:57 +00:00
Don Hinton
f2169e2887 Rollback r319176.
The ';' separators in LLVM_TARGETS_TO_BUILD disappear when list
variables are evaluated in custom commands.

llvm-svn: 319268
2017-11-29 00:47:16 +00:00
Craig Topper
4a0dc124f3 [X86] Promote fp_to_sint v16f32->v16i16/v16i8 to avoid scalarization.
llvm-svn: 319266
2017-11-29 00:32:09 +00:00
Zachary Turner
04cc391642 Fix a warning.
llvm-svn: 319263
2017-11-29 00:13:44 +00:00
Adam Nemet
a8d567ec8e Revert "Add opt-viewer testing"
This reverts commit r319188.

Breaks when c++filt is not available.

llvm-svn: 319262
2017-11-29 00:10:48 +00:00
Craig Topper
a7d54728f8 [X86] Add test cases for fptosi v16f32->v16i8/v16i16 to show scalarization.
llvm-svn: 319261
2017-11-29 00:02:22 +00:00
Zachary Turner
02e8e3f33d [NFC] Minor cleanups in CodeView TypeTableBuilder.
llvm-svn: 319260
2017-11-28 23:57:13 +00:00
Craig Topper
7453e1fa7f [X86] Mark ISD::FP_TO_UINT v16i8/v16i16 as Promote under AVX512 instead of legal. Fix infinite loop in op legalization when promotion requires 2 steps.
Previously we had an isel pattern to add the truncate. Instead use Promote to add the truncate to the DAG before isel.

The Promote legalization code had to be updated to prevent an infinite loop if promotion took multiple steps because it wasn't remembering the previously tried value.

llvm-svn: 319259
2017-11-28 23:56:02 +00:00
Craig Topper
ddc40165bf [X86] Regenerate avx512-schedule test.
For some reason some sqrt instructions were missing the scheduling comments.

llvm-svn: 319258
2017-11-28 23:55:59 +00:00
Matt Arsenault
170d2ed287 AMDGPU: Enable IPRA
llvm-svn: 319256
2017-11-28 23:40:12 +00:00
Simon Pilgrim
7a4d895cdc [X86] Tag CLFLUSHOPT with same scheduling behaviour as CLFLUSH
llvm-svn: 319253
2017-11-28 23:25:42 +00:00
Daniel Sanders
88b4a0878a [globalisel][tablegen] Fix PR35375 by sign-extending the table value to match getConstantVRegVal()
Summary:
From the bug report:
> The problem is that it fails when trying to compare -65536 (or 4294901760) to 0xFFFF,0000. This is because the
> constant in the instruction is sign extended to 64 bits (0xFFFF,FFFF,FFFF,0000) and then compared to the non
> extended 64 bit version expected by TableGen.
> 
> In contrast, the DAGISelEmitter generates special code for AND immediates (OPC_CheckAndImm), which does not
> sign extend.

This patch doesn't introduce the special case for AND (and OR) immediates since the majority of it is related to handling known bits that have no effect on the result and GlobalISel doesn't detect known-bits at this time. Instead this patch just ensures that the immediate is extended consistently on both sides of the check.

Thanks to Diana Picus for the detailed bug report.

Reviewers: rovka

Reviewed By: rovka

Subscribers: kristof.beyls, javed.absar, llvm-commits

Differential Revision: https://reviews.llvm.org/D40532

llvm-svn: 319252
2017-11-28 23:18:54 +00:00
Simon Pilgrim
542dbb0bec [X86] Add CLFLUSHOPT schedule tests
llvm-svn: 319250
2017-11-28 23:12:12 +00:00
Simon Pilgrim
12dfcfe0b1 [X86][SSE] Add SSE_SHUFP OpndItins
Update multi-classes to take the scheduling OpndItins instead of hard coding it.

Will be reused in the AVX512 equivalents.

llvm-svn: 319249
2017-11-28 23:09:18 +00:00
Simon Pilgrim
4850e200a0 [X86] Test clflushopt intrinsic on 32 and 64-bit targets
llvm-svn: 319247
2017-11-28 23:04:42 +00:00
Simon Pilgrim
9e6ca21eca [X86][SSE] Add SSE_UNPCK/SSE_PUNPCK OpndItins
Update multi-classes to take the scheduling OpndItins instead of hard coding it.

Will be reused in the AVX512 equivalents.

llvm-svn: 319245
2017-11-28 22:55:08 +00:00
Simon Pilgrim
3e9942c3b8 [X86][SSE] Use SSE_PACK OpndItins in PACKSS/PACKUS instruction definitions
Update multi-classes to take the scheduling OpndItins instead of hard coding it.

SSE_PACK will be reused in the AVX512 equivalents.

llvm-svn: 319243
2017-11-28 22:47:45 +00:00
Adam Nemet
473eb94bec Remove this test
After r319235, we no longer generate this remark.

llvm-svn: 319242
2017-11-28 22:39:38 +00:00
Simon Pilgrim
79c0ba6d94 Fix VS2017 narrowing conversion warning. NFCI
llvm-svn: 319240
2017-11-28 22:32:43 +00:00
Craig Topper
a16a5768e1 [X86] Remove unused variable.
llvm-svn: 319239
2017-11-28 22:28:23 +00:00
Adam Nemet
4a462917d8 Demote this opt remark to DEBUG.
From a random opt-stat output:

Top 10 remarks:
  tailcallelim/tailcall          53%
  inline/AlwaysInline            13%
  gvn/LoadClobbered              13%
  inline/Inlined                  8%
  inline/TooCostly                2%
  inline/NoDefinition             2%
  licm/LoadWithLoopInvariantAddressInvalidated  2%
  licm/Hoisted                    1%
  asm-printer/InstructionCount    1%
  prologepilog/StackSize          1%

llvm-svn: 319235
2017-11-28 22:11:00 +00:00
Craig Topper
6b120a1adf [X86] Remove code from combineUIntToFP that tried to favor UINT_TO_FP if legal when zero extending from vXi8/vX816.
The UINT_TO_FP is immediately converted to SINT_TO_FP when the node is re-evaluated because we'll detect that the sign bit is zero.

llvm-svn: 319234
2017-11-28 22:08:51 +00:00
Craig Topper
0daab52721 [X86] Remove custom lowering for uint_to_fp from vXi8/vXi16.
We have a DAG combine that uses a zero extend that should prevent this from ever occurring now.

llvm-svn: 319233
2017-11-28 22:08:48 +00:00
Daniel Sanders
ce08391be8 [globalisel][tablegen] Add support for importing G_ATOMIC_CMPXCHG, G_ATOMICRMW_* rules from SelectionDAG.
GIM_CheckNonAtomic has been replaced by GIM_CheckAtomicOrdering to allow it to support a wider
range of orderings. This has then been used to import patterns using nodes such
as atomic_cmp_swap, atomic_swap, and atomic_load_*.

llvm-svn: 319232
2017-11-28 22:07:05 +00:00
Adrian Prantl
ee6ecd60f5 SROA: Don't create variable fragments that are outside of the variable.
An alloca may be larger than a variable that is described to be stored
there. Don't create a dbg.value for fragments that are outside of the
variable.

This fixes PR35447.
https://bugs.llvm.org/show_bug.cgi?id=35447

llvm-svn: 319230
2017-11-28 21:30:38 +00:00
Don Hinton
57f9a6b164 [cmake] Pass LLVM_USE_LINKER flag when building host tools, e.g.,
LLVM_OPTIMIZED_TABLEGEN=ON, and not crosscompiling.

Differential Revision: https://reviews.llvm.org/D39734

llvm-svn: 319228
2017-11-28 21:23:30 +00:00
Alexey Bataev
6450563023 [SLP] Additional test for PR35354, NFC.
llvm-svn: 319224
2017-11-28 20:48:24 +00:00
Mandeep Singh Grang
8acd316e73 [Hexagon] Use stable sort for HexagonShuffler to remove non-deterministic ordering
Summary:
This fixes failures in the following tests uncovered by D39245:
        LLVM :: CodeGen/Hexagon/args.ll
        LLVM :: CodeGen/Hexagon/constp-extract.ll
        LLVM :: CodeGen/Hexagon/expand-condsets-basic.ll
        LLVM :: CodeGen/Hexagon/gp-rel.ll
        LLVM :: CodeGen/Hexagon/packetize_cond_inst.ll
        LLVM :: CodeGen/Hexagon/simple_addend.ll
        LLVM :: CodeGen/Hexagon/swp-stages4.ll
        LLVM :: CodeGen/Hexagon/swp-vmult.ll
        LLVM :: CodeGen/Hexagon/swp-vsum.ll
        LLVM :: MC/Hexagon/align.s
        LLVM :: MC/Hexagon/asmMap.s
        LLVM :: MC/Hexagon/dis-duplex-p0.s
        LLVM :: MC/Hexagon/double-vector-producer.s
        LLVM :: MC/Hexagon/inst_select.ll
        LLVM :: MC/Hexagon/instructions/j.s

Reviewers: colinl, kparzysz, adasgupt, slarin

Reviewed By: kparzysz

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D40227

llvm-svn: 319223
2017-11-28 20:48:10 +00:00
Daniel Sanders
ded67ff6bb [aarch64][globalisel] Add missing tests from r319216
llvm-svn: 319220
2017-11-28 20:27:59 +00:00