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Commit Graph

218001 Commits

Author SHA1 Message Date
Nico Weber
856c1b08d5 [gn build] Port 050b064f15ee 2021-07-01 14:52:21 -04:00
Nikita Popov
460a9b9357 [OpaquePtr] Support VecOfAnyPtrsToElt intrinsics
In this case the pointer type is part of the mangled name, so we
can allow on opaque pointer outside --force-opaque-pointers mode
as well.
2021-07-01 20:35:33 +02:00
Scott Linder
62d5b36f28 [ADT] Follow up to fix bug in "Add makeVisitor to STLExtras.h"
Address mistakenly comparing the pointer values of two C-style strings
rather than comparing their contents in the unit tests for makeVisitor,
added in 6d6f35eb7b92c6dd4478834497752f4e963db16d
2021-07-01 18:24:49 +00:00
Philip Reames
ade0ec7fb0 [instcombine] Fold overflow check using overflow intrinsic to comparison
This follows up to D104665 (which added umulo handling alongside the existing uaddo case), and generalizes for the remaining overflow intrinsics.

I went to add analogous handling to LVI, and discovered that LVI already had a more general implementation. Instead, we can port was LVI does to instcombine. (For context, LVI uses makeExactNoWrapRegion to constrain the value 'x' in blocks reached after a branch on the condition `op.with.overflow(x, C).overflow`.)

Differential Revision: https://reviews.llvm.org/D104932
2021-07-01 09:41:55 -07:00
Nikita Popov
6203a57d08 [OpaquePtr] Support opaque pointers in intrinsic type check
This adds support for opaque pointers in intrinsic type checks
of IIT kind Pointer and PtrToElt.

This is less straight-forward than it might initially seem, because
we should only accept opaque pointers here in --force-opaque-pointers
mode. Otherwise, there would be more than one valid type signature
for a given intrinsic name.

Differential Revision: https://reviews.llvm.org/D105155
2021-07-01 18:26:41 +02:00
Matt Arsenault
20d89b9242 GlobalISel: Use LLT in call lowering callbacks
This preserves the memory type so the lowerings can rely on them.
2021-07-01 12:15:54 -04:00
Bradley Smith
f53921a516 [SelectionDAG] Implement PromoteIntRes_INSERT_SUBVECTOR
Inserting into a smaller-than-legal scalable vector would result in an
internal compiler error. For example, inserting a <vscale x 4 x i8> into
a <vscale x 8 x i8> (both illegal vector types for SVE) would cause a
crash.

This crash was happening because there was no code to promote (legalise)
the result of an INSERT_SUBVECTOR node.

This patch implements PromoteIntRes_INSERT_SUBVECTOR, which legalises
the ISD node. This is currently done by going through memory. This is
necessary because of the requirement that the SubVec parameter of the
INSERT_SUBVECTOR node must be smaller than the Vec parameter, which
means that INSERT_SUBVECTOR cannot always have a legal result/operand
types.

Co-Authored-by: Joe Ellis <joe.ellis@arm.com>

Differential Revision: https://reviews.llvm.org/D102766
2021-07-01 17:05:53 +01:00
Stanislav Mekhanoshin
bb5a67dc29 [AMDGPU] Fix immediate sign during V_MOV_B64_PSEUDO expansion
Creating a V_MOV_B32 with zero extended immediate source
prevented conversion to V_BFREV_B32.

Differential Revision: https://reviews.llvm.org/D105235
2021-07-01 09:00:29 -07:00
David Green
878abea094 [ARM] Extra BFI codegen tests. NFC 2021-07-01 16:56:23 +01:00
Irina Dobrescu
b31f0d013b [AArch64][GlobalISel]Legalise some vector types for min/max
Differential Revision: https://reviews.llvm.org/D105200
2021-07-01 16:29:38 +01:00
Nico Weber
394ac62585 [clangd] Unbreak mac build differently 0c96a92d8666b8
This reverts b56e5f8a10c1 (and follow-up f6db88535cb) and instead
restores the state we had before 0c96a92d8666b8: ClangdMain.cpp
includes Features.inc before including Transport.h.

This is a bit ugly, but it matches the former state and making Transport.h
include Features.h means that xpc/ needs to be able to find the generated
Features.inc, wich is also a bit ugly.
2021-07-01 10:51:27 -04:00
Simon Pilgrim
adc36a317c [LoopVectorize][X86] Regenerate conversion-cost.ll tests 2021-07-01 15:34:20 +01:00
Simon Pilgrim
f0a2f7f0f9 [CostModel][X86] Adjust fp<->int vXi32 SSE legalized costs based on llvm-mca reports.
Building on rG2a1ef8784ad9a, adjust the SSE cost tables to use the legalized types based on the worst case costs from the script in D103695.

To account for different numbers of src/dst legalized type registers we must scale the cost by maximum of the src/dst, not just use src
2021-07-01 15:34:20 +01:00
Arnold Schwaighofer
10d39b09ad [coro async] Add support for specifying which parameter is swiftself in
async resume functions

Differential Revision: https://reviews.llvm.org/D104147
2021-07-01 07:33:15 -07:00
Sjoerd Meijer
db79ea7a1b [AArch64] Add some more tests to CodeGen/AArch64/aarch64-load-ext.ll. NFC. 2021-07-01 15:15:21 +01:00
Sam Tebbs
5e767994e1 [ARM] Transform a floating-point to fixed-point conversion to a VCVT_fix
Much like fixed-point to floating-point conversion, the converse can
also be transformed into a fixed-point VCVT. This patch transforms
multiplications of floating point numbers by 2^n into a VCVT_fix. The
exception is that a float to fixed conversion with 1 fractional bit
ends up being an FADD (FADD(x, x) emulates FMUL(x, 2)) rather than an FMUL so there is a special case for that. This patch also moves the code from https://reviews.llvm.org/D103903 into a separate function as fixed to float and float to fixed are very similar.

Differential Revision: https://reviews.llvm.org/D104793
2021-07-01 15:10:40 +01:00
David Sherwood
83f2bbd3b5 [NFC] Add new setDebugLocFromInst that uses the class Builder by default
In lots of places we were calling setDebugLocFromInst and passing
in the same Builder member variable found in InnerLoopVectorizer.
I personally found this confusing so I've changed the interface
to take an Optional<IRBuilder<> *> and we can now pass in None
when we want to use the class member variable.

Differential Revision: https://reviews.llvm.org/D105100
2021-07-01 14:23:34 +01:00
Florian Hahn
edf84d3cd7 [AArch64] Add fp16 tests for vector copysign.
Add additional fp16 vector tests for copysign, to show improvements in
follow-up patch.
2021-07-01 13:54:06 +01:00
Irina Dobrescu
23b1856602 [AArch64] Add test for min/max
Differential Revision: https://reviews.llvm.org/D104447
2021-07-01 13:22:51 +01:00
Jeremy Morse
094b01ebbc [DebugInfo][InstrRef][2/4] Use subreg substitutions in LiveDebugValues
Added in 47c3fe2a22cf, we sometimes need to describe a variable value
substitution with a subregister qualifier, to say that "the value is the
lower 32 bits of this 64 bit register def" for example. That then needs
support during LiveDebugValues to interpret the subregister qualifiers,
which is what this patch adds.

Whenever we encounter a DBG_INSTR_REF and find its value by using a
substitution, collect any subregister qualifiers seen. Then, accumulate the
effects of the qualifiers to work out what offset and what size should be
extracted from the defined register. Finally, for the target ValueIDNum,
extract whatever subregister is in the correct position

Currently, describing a subregister field of a larger value that has been
spilt to the stack, is unimplemented.

Differential Revision: https://reviews.llvm.org/D88894
2021-07-01 13:07:16 +01:00
Marcos Horro
a240604c37 [llvm-mca] Fix JSON output (PR50922)
Based on the discussion in PR50922, minor changes have been done to properly
output a valid JSON.  Removed "not implemented" keys.

Differential Revision: https://reviews.llvm.org/D105064
2021-07-01 12:53:20 +01:00
Hussain Kadhem
7eddb43fa0 [VP] Implementation of intrinsic and SDNode definitions for VP load, store, gather, scatter.
This patch adds intrinsic definitions and SDNodes for predicated
load/store/gather/scatter, based on the work done in D57504.

Reviewed By: simoll, craig.topper

Differential Revision: https://reviews.llvm.org/D99355
2021-07-01 13:34:44 +02:00
Bradley Smith
e07552eb3f [AArch64][SVE] Add support for fixed length MSCATTER/MGATHER
Since gather lowering can now lower to nodes that may need expansion via
the vector legalizer, do MGATHER lowering via vector legalizer.

Additionally, as part of adding passthru support for fixed typed
gathers, fix passthru support for scalable types.

Depends on D104910

Differential Revision: https://reviews.llvm.org/D104217
2021-07-01 12:13:59 +01:00
David Spickett
d59877b7e5 [llvm][docs] Bump release number from 12 -> 13
This seems to have been forgotten. The result was the title
of pages like https://llvm.org/docs/ReleaseNotes.html

Was:
<title>LLVM 13.0.0 Release Notes &#8212; LLVM 12 documentation</title>

Reviewed By: tstellar

Differential Revision: https://reviews.llvm.org/D105189
2021-07-01 11:07:03 +00:00
Simon Pilgrim
b53b3c8d1c [CostModel][X86] getCastInstrCost - attempt to match custom cast/conversion before legalized types.
Move the (SSE-only) generic, legalized type conversion matching after the specific,custom conversion cases, allowing us to properly provide cost overrides.

The next step will be to clean up some of the weird existing costs and then to enable AVX+ legalized costs, which will let us strip out a lot of the cost tables entries.
2021-07-01 12:06:40 +01:00
Jeremy Morse
7a8e30eba0 [DebugInfo][InstrRef][1/4] Support transformations that widen values
Very late in compilation, backends like X86 will perform optimisations like
this:

    $cx = MOV16rm $rax, ...
    ->
    $rcx = MOV64rm $rax, ...

Widening the load from 16 bits to 64 bits. SEeing how the lower 16 bits
remain the same, this doesn't affect execution. However, any debug
instruction reference to the defined operand now refers to a 64 bit value,
nto a 16 bit one, which might be unexpected. Elsewhere in codegen, there's
often this pattern:

    CALL64pcrel32 @foo, implicit-def $rax
    %0:gr64 = COPY $rax
    %1:gr32 = COPY %0.sub_32bit

Where we want to refer to the definition of $eax by the call, but don't
want to refer the copies (they don't define values in the way
LiveDebugValues sees it). To solve this, add a subregister field to the
existing "substitutions" facility, so that we can describe a field within
a larger value definition. I would imagine that this would be used most
often when a value is widened, and we need to refer to the original,
narrower definition.

Differential Revision: https://reviews.llvm.org/D88891
2021-07-01 11:19:27 +01:00
Christian Kühnel
70970300a3 added some example code for llvm::Expected<T>
Since I had some fun understanding how to properly use llvm::Expected<T> I added some code examples that I would have liked to see when learning to use it.

Reviewed By: sammccall

Differential Revision: https://reviews.llvm.org/D105014
2021-07-01 09:57:20 +00:00
Chen Zheng
1e191e2f0c [PowerPC] add a testcase for byval parameter; NFC 2021-07-01 09:42:12 +00:00
Florian Hahn
378b11e2da [BasicAA] Fix typo ScaleForGDC -> ScaleForGCD. 2021-07-01 09:58:38 +01:00
LLVM GN Syncbot
81673f2df8 [gn build] Port 39f64c4c8375 2021-07-01 08:31:00 +00:00
Andrzej Warzynski
41a27c03c7 [flang] Revert "PoC for Flang Driver Plugins"
This patch has not been reviewed and was commited by accident.

This reverts commit 788a5d4afe6407e647454a9832a7b4a27fba06bf.
2021-07-01 08:27:31 +00:00
Lang Hames
6567b76038 [ORC] Add wrapper-function support methods to ExecutorProcessControl.
Adds support for both synchronous and asynchronous calls to wrapper functions
using SPS (Simple Packed Serialization). Also adds support for wrapping
functions on the JIT side in SPS-based wrappers that can be called from the
executor.

These new methods simplify calls between the JIT and Executor, and will be used
in upcoming ORC runtime patches to enable communication between ORC and the
runtime.
2021-07-01 18:21:49 +10:00
Stuart Ellis
c930f37268 PoC for Flang Driver Plugins 2021-07-01 08:10:40 +00:00
Roman Lebedev
e9c11e84f4 [NFC][PassBuilder] addVectorPasses(): clarify that 'IsLTO' is actually 'IsFullLTO'
I.e. it will be `false` for thin lto.
2021-07-01 10:09:24 +03:00
Qiu Chaofan
a315353f43 [NFC][Scheduler] Refactor tryCandidate to return boolean
This patch changes return type of tryCandidate from void to bool:

1. Methods in some targets already follow this convention.
2. This would help if some target wants to re-use generic code.
3. It looks more intuitive if these try-method returns the same type.

We may need to change return type of them from bool to some enum
further, to make it less confusing.

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D103951
2021-07-01 14:31:47 +08:00
Jacob Hegna
15460e3887 Fail gracefully if no inlining model is available to download.
Differential Revision: https://reviews.llvm.org/D104829
2021-07-01 04:04:11 +00:00
LLVM GN Syncbot
4a2c6265d9 [gn build] Port 28b01c59c93d 2021-07-01 04:00:13 +00:00
LLVM GN Syncbot
d69d14b00d [gn build] Port 662c55442f17 2021-07-01 03:45:41 +00:00
Lang Hames
a397416183 [ORC] Rename TargetProcessControl to ExecutorProcessControl. NFC.
This is a first step towards consistently using the term 'executor' for the
process that executes JIT'd code. I've opted for 'executor' as the preferred
term over 'target' as target is already heavily overloaded ("the target
machine for the executor" is much clearer than "the target machine for the
target").
2021-07-01 13:31:12 +10:00
Chuanqi Xu
2866155d9f [Coroutine] Recommit Add statistics for the number of elided coroutine
Now we lack a benchmark to measure the performance change for each
commit.
Since coro elide is the main optimization in coroutine module, I wonder
it may be an estimation to count the number of elided coroutine in
private code bases.
e.g., for a certain commit, if we found that the number of elided goes
down, we could find it before the commit check-in.

Reviewed By: lxfind

Differential Revision: https://reviews.llvm.org/D105095
2021-07-01 11:01:28 +08:00
Jez Ng
69e52cdafc [llvm-objdump/mac] Print symbols at the same address deterministically
By using stable_sort.

Added a test case which previously failed when expensive checks were
enabled.

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D105240
2021-06-30 22:38:07 -04:00
Jun Ma
e735ac1e0d [AArch64][SVEIntrinsicOpts] Convect cntb/h/w/d to vscale intrinsic or constant.
As is mentioned above

Differential Revision: https://reviews.llvm.org/D104852
2021-07-01 10:09:47 +08:00
Fangrui Song
ecb5bd2ec9 [AArch64] Remove unneeded ExternalSymbolSDNode code for machine constraint "S". NFC
ExternalSymbolSDNode is implicitly generated libcalls but with an address taking
operation we cannot reference an ExternalSymbolSDNode.
2021-06-30 17:52:56 -07:00
Min-Yih Hsu
bd501a8115 Reapply "[M68k][GloballSel] Formal arguments lowering in IRTranslator"
Implementation of formal arguments lowering in the IRTranslator for the
M68k backend

Differential Revision: https://reviews.llvm.org/D104542
2021-06-30 17:13:45 -07:00
Sanjay Patel
7e45dc58a5 [InstCombine] fold icmp ult of offset value with constant
This is one sibling of the fold added with c7b658aeb526 .

(X + C2) <u C --> X >s ~C2 (if C == C2 + SMIN)
I'm still not sure how to describe it best, but we're
translating 2 constants from an unsigned range comparison
to signed because that eliminates the offset (add) op.

This could be extended to handle the more general (non-constant)
pattern too:
https://alive2.llvm.org/ce/z/K-fMBf

  define i1 @src(i8 %a, i8 %c2) {
    %t = add i8 %a, %c2
    %c = add i8 %c2, 128 ; SMIN
    %ov = icmp ult i8 %t, %c
    ret i1 %ov
  }

  define i1 @tgt(i8 %a, i8 %c2) {
    %not_c2 = xor i8 %c2, -1
    %ov = icmp sgt i8 %a, %not_c2
    ret i1 %ov
  }
2021-06-30 19:00:12 -04:00
Sanjay Patel
7797df93d6 [InstCombine][test] add tests for icmp ult with constant and offset; NFC
This is the 'ult' sibling pattern for:
c7b658aeb526c3e6
2021-06-30 19:00:12 -04:00
Jeremy Morse
c57016fd83 [LiveDebugValues][InstrRef][2/2] Emit entry value variable locations
This patch adds support to the instruction-referencing LiveDebugValues
implementation for emitting entry values. The instruction referencing
implementations tracking by value rather than location means that we can
get around two of the issues with VarLocs. DBG_VALUE instructions that
re-assign the same value to a variable are no longer a problem, because we
can "see through" to the value being assigned. We also don't need to do
anything special during the dataflow stages: the "variable value problem"
doesn't need to know whether a value is available most of the time, and the
times it deoes need to know are always when entry values need to be
terminated.

The patch modifies the "TransferTracker" class, adding methods to identify
when a variable ias an entry value candidate, and when a machine value is
an entry value. recoverAsEntryValue tests these two things and emits an
entry-value expression if they're true. It's used when we clobber or
otherwise lose a value and can't find a replacement location for the value
it contained.

Differential Revision: https://reviews.llvm.org/D88406
2021-06-30 23:07:39 +01:00
Matt Arsenault
d665475981 GlobalISel: Use LLT in memory legality queries
This enables proper lowering of non-byte sized loads. We still aren't
faithfully preserving memory types everywhere, so the legality checks
still only consider the size.
2021-06-30 17:44:13 -04:00
Matt Arsenault
9526df50fa GlobalISel: Lower non-byte loads and stores
Previously we didn't preserve the memory type and had to blindly
interpret a number of bytes. Now that non-byte memory accesses are
representable, we can handle these correctly.

Ported from DAG version (minus some weird special case i1 legality
checking which I don't fully understand, and we don't have a way to
query for)

For now, this is NFC and the test changes are placeholders. Since the
legality queries are still relying on byte-flattened memory sizes, the
legalizer can't actually see these non-byte accesses. This keeps this
change self contained without merging it with the larger patch to
switch to LLT memory queries.
2021-06-30 17:05:50 -04:00
Matt Arsenault
59f5d684fb GlobalISel: Preserve memory type when reducing load/store width 2021-06-30 17:05:29 -04:00