4 Commits

Author	SHA1	Message	Date
Michael Liao	349e772e4f	More rewrites of x86 codegen regression tests with FileCheck ... llvm-svn: 180837	2013-05-01 05:34:30 +00:00
Dan Gohman	df2896d609	Eliminate more uses of llvm-as and llvm-dis. ... llvm-svn: 81290	2009-09-08 23:54:48 +00:00
Dan Gohman	5f6f8101d5	Split the Add, Sub, and Mul instruction opcodes into separate ... integer and floating-point opcodes, introducing FAdd, FSub, and FMul. For now, the AsmParser, BitcodeReader, and IRBuilder all preserve backwards compatability, and the Core LLVM APIs preserve backwards compatibility for IR producers. Most front-ends won't need to change immediately. This implements the first step of the plan outlined here: http://nondot.org/sabre/LLVMNotes/IntegerOverflow.txt llvm-svn: 72897	2009-06-04 22:49:04 +00:00
Evan Cheng	a70ecc2f51	The coalescer does not coalesce a virtual register to a physical register if any of the physical register's sub-register live intervals overlaps with the virtual register. This is overly conservative. It prevents a extract_subreg from being coalesced away: ... v1024 = EDI // not killed = = EDI One possible solution is for the coalescer to examine the sub-register live intervals in the same manner as the physical register. Another possibility is to examine defs and uses (when needed) of sub-registers. Both solutions are too expensive. For now, look for "short virtual intervals" and scan instructions to look for conflict instead. This is a small win on x86-64. e.g. It shaves 403.gcc by ~80 instructions. llvm-svn: 61847	2009-01-07 02:08:57 +00:00