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Commit Graph

203969 Commits

Author SHA1 Message Date
Florian Hahn
77b449d743 Recommit "[SCEV] Look through single value PHIs."
This commit was originally because it was suspected to cause a crash,
but a reproducer did not surface.

A crash that was exposed by this change was fixed in 1d8f2e52925b.

This reverts the revert commit 0581c0b0eeba03da590d1176a4580cf9b9e8d1e3.
2020-09-21 11:59:50 +01:00
David Green
c8c6d59c71 [ARM] Select f32 constants with vmov.f16
This adds lowering for f32 values using the vmov.f16, which zeroes the
top bits whilst setting the lower bits to a pattern. This range of
values does not often come up, except where a f16 constant value has
been converted to a f32.

Differential Revision: https://reviews.llvm.org/D87790
2020-09-21 11:10:47 +01:00
Georgii Rymar
3caa549f90 [llvm-readelf/obj] - Stop printing invalid names for unnamed section symbols.
We have an issue with `ELFDumper<ELFT>::getSymbolSectionName`:
1) It is used deeply for both LLVM/GNU styles and might return LLVM-style only
   values to describe symbols: "Undefined", "Processor Specific", "Absolute", etc.

2) `getSymbolSectionName` is used by `getFullSymbolName` and these special values
   might appear instead of symbol names in many places.
   This occurs for unnamed section symbols currently.

This patch extracts the LLVM specific logic to `LLVMStyle<ELFT>::printSymbolSection`,
which seems to be the only place where we want to print the special values mentioned.
It also adds a meaningful new warning that is reported when we are unable to get
a section index for a section symbol.

Differential revision: https://reviews.llvm.org/D87764
2020-09-21 13:05:46 +03:00
Sam Parker
a9b02cf295 [NFC][ARM] More tail predication tests.
Add mir tests for use/def of P0.
2020-09-21 10:58:05 +01:00
Sjoerd Meijer
622615c7ad [AArch64] Cortex-A55 scheduler model
This is an initial commit adding the A55 model, but it isn't used/enabled yet.
We will follow up on this to improve the model, then flip the switch.

The optimisation guide describing Cortex-A55 micro-architecture in more detail
can be found here:

https://static.docs.arm.com/epm128372/20/arm_cortex_a55_software_optimization_guide_v2.pdf

Original patch by Javed Absar.

Differential Revision: https://reviews.llvm.org/D46884
2020-09-21 10:54:32 +01:00
Alex Richardson
01addf8046 [RISC-V] Implement RISCVInstrInfo::isCopyInstrImpl()
This does not result in changes for any of the current tests, but it might
improve debug information in some cases.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D86522
2020-09-21 10:21:11 +01:00
Max Kazantsev
562da2bbfa [Test] Test auto-update 2020-09-21 16:06:18 +07:00
Lucas Prates
438b0e34bd [CodeGen] Fixing inconsistent ABI mangling of vlaues in SelectionDAGBuilder
SelectionDAGBuilder was inconsistently mangling values based on ABI
Calling Conventions when getting them through copyFromRegs in
SelectionDAGBuilder, causing duplicate value type convertions for
function arguments. The checking for the mangling requirement was based
on the value's originating instruction and was performed outside of, and
inspite of, the regular Calling Convention Lowering.

The issue could be observed in a scenario such as:

```
%arg1 = load half, half* %const, align 2
%arg2 = call fastcc half @someFunc()
call fastcc void @otherFunc(half %arg1, half %arg2)
; Here, %arg2 was incorrectly mangled twice, as the CallConv data from
; the call to @someFunc() was taken into consideration for the check
; when getting the value for processing the call to @otherFunc(...),
; after the proper convertion had taken place when lowering the return
; value of the first call.
```

This patch fixes the issue by disregarding the Calling Convention
information for such copyFromRegs, making sure the ABI mangling is
properly contanined in the Calling Convention Lowering.

This fixes Bugzilla #47454.

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D87844
2020-09-21 10:05:34 +01:00
Florian Hahn
fe09f259f9 [LSR] Preserve MSSA when using SplitCriticalEdge.
LSR claims to MemorySSA, but we also have to make sure it is preserved
when splitting critical edges. This can be done by passing MSSAU to
SplitCriticalEdge.

Fixes PR47557.
2020-09-21 09:51:26 +01:00
Fangrui Song
e6e7c80f0e [EHStreamer] Fix a "Continue to action" -fverbose-asm comment when multi-byte LEB128 encoding is needed
This only happens with more than 64 action records and it is difficult to construct a test.
2020-09-20 21:41:48 -07:00
Qiu Chaofan
d6e49b7d70 [PowerPC] Pass nofpexcept flag to custom lowered constrained ops
This is a follow-up of D86605. For strict DAG FP node, if its FP
exception behavior metadata is ignore, it should have nofpexcept flag.
But during custom lowering, this flag isn't passed down.

This is also seen on X86 target.

Reviewed By: uweigand

Differential Revision: https://reviews.llvm.org/D87390
2020-09-21 10:44:25 +08:00
Fangrui Song
4dabbec93d [XRay] Change mips to use version 2 sled (PC-relative address)
Follow-up to D78590. All targets use PC-relative addresses now.

Reviewed By: atanasyan, dberris

Differential Revision: https://reviews.llvm.org/D87977
2020-09-20 17:59:57 -07:00
wlei
e56a524153 [llvm-profdata]Fix llvm-profdata crash on compact binary profile
llvm-profdata `show` and `overlap` will crash in `getFuncName` on compact binary profile. This change fixed this by switching to use `getName`.

 `getFuncName` is misused in llvm-profdata. As showed below, `GUIDToFuncNameMap` is only supported in compilation mode, there is no initialization in llvm-profdata. Compact profile whose MD5 is true would try to query `GUIDToFuncNameMap` then caused the crash. So fix this by switching to `getName`

Reviewed By: MaskRay, wmi, wenlei, weihe, hoy

Differential Revision: https://reviews.llvm.org/D87740
2020-09-20 16:58:34 -07:00
Craig Topper
634488ce52 [X86] Make reduceMaskedLoadToScalarLoad/reduceMaskedStoreToScalarStore work for avx512 after type legalization.
The scalar elements of the vXi1 build_vector will have been type legalized to i8 by padding with 0s. So we can't check for all ones. Instead we should just look at bit 0 of the constant.

Differential Revision: https://reviews.llvm.org/D87863
2020-09-20 13:54:20 -07:00
Craig Topper
5cf94a6388 [X86] Pre-commit test cases for D87863. NFC 2020-09-20 13:53:05 -07:00
Craig Topper
aa3ccaf198 [X86] Stop reduceMaskedLoadToScalarLoad/reduceMaskedStoreToScalarStore from creating scalar i64 load/stores in 32-bit mode
If we emit a scalar i64 load/store it will get type legalized to two i32 load/stores.

Differential Revision: https://reviews.llvm.org/D87862
2020-09-20 13:46:59 -07:00
Craig Topper
b826feba37 [X86] Add 32-bit command lines to masked_store.ll and masked_load.ll 2020-09-20 13:46:59 -07:00
David Green
aa89df6c4c [ARM] Constant fold VMOVrh
This adds simple constant folding for VMOVrh, to constant fold fp16
constants to integer values. It can help especially with soft calling
conventions, but some of the results are not optimal as we end up
loading using a vldr. This will be improved in a follow up patch.

Differential Revision: https://reviews.llvm.org/D87789
2020-09-20 21:32:51 +01:00
Nikita Popov
f5e86efea8 [CVP] Additional tests for comparison with offset (NFC)
Both icmps have an additional offset here. We would fold this if
the second one didn't.
2020-09-20 22:10:34 +02:00
Nikita Popov
766062255a [LVI] Get value range from mask comparison
InstCombine likes to canonicalize comparisons of the form
X == C || X == C+1 into (X & -2) == C'. Make sure LVI can still
recover the value range from this. Can of course also be useful
for proper mask comparisons.

For the sake of clarity, the implementation goes through KnownBits
to compute the range.
2020-09-20 21:13:57 +02:00
Nikita Popov
cdfdf3ce65 [CVP] Add tests for mask comparisons (NFC) 2020-09-20 21:13:57 +02:00
Nikita Popov
e0082e6dcf [LVI] Refactor getValueFromICmpCondition (NFC)
Rewrite this in a way where the core logic is in a separate
function, that is invoked with swapped operands. This makes it
easier to add handling for additional icmp patterns.
2020-09-20 21:13:57 +02:00
Simon Pilgrim
228d97b26d [X86][SSE] Fold EXTEND_VECTOR_INREG(EXTRACT_SUBVECTOR(EXTEND(X),0)) -> EXTEND_VECTOR_INREG(X) 2020-09-20 18:39:12 +01:00
Simon Pilgrim
19d99cd594 [X86][SSE] Fold SIGN_EXTEND(SIGN_EXTEND_VECTOR_INREG(X)) -> SIGN_EXTEND_VECTOR_INREG(X)
It should be possible to make this generic, but we're not great at checking legality of *_EXTEND_VECTOR_INREG ops so I'm conservatively putting this inside X86ISelLowering.cpp
2020-09-20 18:39:12 +01:00
Sanjay Patel
79a8f1c79c [InstCombine] factorize left shifts of add/sub
We do similar factorization folds in SimplifyUsingDistributiveLaws,
but that drops no-wrap properties. Propagating those optimally may
help solve:
https://llvm.org/PR47430

The propagation is all-or-nothing for these patterns: when all
3 incoming ops have nsw or nuw, the 2 new ops should have the
same no-wrap property:
https://alive2.llvm.org/ce/z/Dv8wsU

This also solves:
https://llvm.org/PR47584
2020-09-20 12:55:24 -04:00
Sanjay Patel
2991bca580 [InstCombine] replace zombie unreachable values with 'undef' before erasing
The test (currently crashing) is reduced from the example provided
in the post-commit discussion in D87149.

Differential Revision: https://reviews.llvm.org/D87965
2020-09-20 12:25:08 -04:00
Simon Pilgrim
178cee9086 [X86][SSE] Fold EXTEND_VECTOR_INREG(EXTEND_VECTOR_INREG(X)) -> EXTEND_VECTOR_INREG(X)
It should be possible to make this generic, but we're not great at checking legality of *_EXTEND_VECTOR_INREG ops so I'm conservatively putting this inside X86ISelLowering.cpp
2020-09-20 16:33:02 +01:00
Simon Pilgrim
66a7dfdc0c [X86][SSE] Enable ZERO_EXTEND_VECTOR_INREG shuffle combining on SSE41 targets.
Allows ZERO_EXTEND_VECTOR_INREG to be shuffle combined on all targets where it is legal.
2020-09-20 16:05:10 +01:00
Simon Pilgrim
c44544f40e [X86] Rename getExtendInVec to getEXTEND_VECTOR_INREG. NFCI.
Make it easier to find the method by naming it after the ops it actually handles. We already do this for lowering/combining.
2020-09-20 15:19:39 +01:00
Simon Pilgrim
c10f7482f0 DWARFYAML::emitDebugSections - fix use after std::move warnings. NFCI.
We were using Err after it had been moved into cantFail - avoid this by calling cantFail with Error::success() directly.
2020-09-20 14:42:36 +01:00
Simon Pilgrim
b9b03a71fd [X86] combineX86ShufflesRecursively - fix use after move warning. NFCI.
After moving WidenedMask is in an undefined state, so reduce scope of the variable so its reinitialized every iteration - we should still retain any memory allocation savings.
2020-09-20 14:06:50 +01:00
Dávid Bolvanský
fe83462295 [MemLoc] Support lllvm.memcpy.inline in MemoryLocation::getForArgument
Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D87971
2020-09-20 14:01:48 +02:00
Simon Pilgrim
0e960b0556 [X86] Rename combineExtInVec to combineEXTEND_VECTOR_INREG. NFCI.
Make it easier to find the method by naming it after the ops it actually handles. We already do this for lowering.
2020-09-20 12:16:00 +01:00
Rainer Orth
4d957ca492 [tools][remarks-shlib] Don't build libRemarks.so without PIC
A build on `sparcv9-sun-solaris2.11` with `-DLLVM_ENABLE_PIC=Off` failed
linking `libRemarks.so`:

  [27/2297] Linking CXX shared library lib/libRemarks.so.12git
  FAILED: lib/libRemarks.so.12git
  [...]
  ld: fatal: relocation error: R_SPARC_H44: file lib/libLLVMRemarks.a(Remark.cpp.o): symbol _ZTVN4llvm18raw_string_ostreamE: invalid shared object relocation type: ABS44 code model unsupported
  [...]

On Solaris/sparcv9 as on many other targets you cannot link non-PIC objects
into a shared object.

The following patch avoids this by not building the library with PIC.  It
allowed the build to complete and `ninja check-all` showed no errors.

Differential Revision: https://reviews.llvm.org/D85626
2020-09-20 12:40:21 +02:00
Fangrui Song
acda854fa5 [FunctionAttrs] Inline setDoesNotRecurse() and delete it. NFC
It always returns true, which may lead to confusion. Inline it because it is
trivial and only called twice.
2020-09-19 22:24:52 -07:00
Fangrui Song
2485eebd4f [FunctionAttrs] Remove redundant check. NFC 2020-09-19 20:46:18 -07:00
Fangrui Song
64799c106c Fix some clang-tidy bugprone-argument-comment issues 2020-09-19 20:41:25 -07:00
Lang Hames
6ab9d78a52 [ORC][examples] Add an OrcV2 example for IR optimization via IRTransformLayer.
Shows how to write a custom IR transform to apply a legacy::PassManager
pipeline.
2020-09-19 18:59:52 -07:00
Nikita Popov
2428bdcb45 [Local] Clean up enforceKnownAlignment() (NFC)
I want to export this function, and the current API was a bit
weird: It took an additional Alignment argument that didn't really
have anything to do with what the function does. Drop it, and
perform a max at the callsite.

Also rename it to tryEnforceAlignment().
2020-09-19 22:29:40 +02:00
Nikita Popov
5a88990a71 [InstCombine] Regenerate test checks (NFC) 2020-09-19 21:07:54 +02:00
Roman Lebedev
4c7d81897d [NFC][PhaseOrdering] Add test showing SROA not being performed after loop unrolling 2020-09-19 21:18:35 +03:00
Dávid Bolvanský
7aaf91a742 [BasicAA] Regenerate test checks 2020-09-19 19:36:10 +02:00
Florian Hahn
03e16aab4f [SCEVExpander] Support expanding nonintegral pointers with constant base.
Currently SCEVExpander creates inttoptr for non-integral pointers if the
base is a null constant for example. This results in invalid IR.

This patch changes InsertNoopCastOfTo to emit a GEP & bitcast to convert
to a non-integral pointer. First, a GEP of i8* null is generated and the
integral value is used as index. The GEP is then bitcasted to the target
type.

This was exposed by D71539.

Reviewed By: efriedma

Differential Revision: https://reviews.llvm.org/D87827
2020-09-19 17:19:53 +01:00
Dávid Bolvanský
0126c354e7 [MemLoc] Support bcmp in MemoryLocation::getForArgument
Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D87964
2020-09-19 17:12:43 +02:00
Sanjay Patel
7799c41807 [InstCombine] auto-generate test checks; NFC 2020-09-19 11:06:47 -04:00
Sanjay Patel
c6580be685 [InstCombine] regenerate test checks; NFC 2020-09-19 10:43:18 -04:00
Sanjay Patel
883809adba [ConstantFolding] add undef handling for fmin/fmax intrinsics
The output here may not be optimal (yet), but it should be
consistent for commuted operands (it was not before) and
correct. We can do better by checking FMF and NaN if needed.

Code in InstSimplify generally assumes that we have already
folded code like this, so it was not handling 2 constant
inputs by commuting consistently.
2020-09-19 10:31:01 -04:00
Paul C. Anagnostopoulos
58f51bc97c Change name of Record::TheInit to CorrespondingDefInit to make code clearer.
Differential Revision: https://reviews.llvm.org/D87919
2020-09-19 09:18:44 -04:00
Nico Weber
fa66d9af58 [gn build] Port 2124ca1d5cb 2020-09-19 08:34:58 -04:00
Nico Weber
d4bdf8df2e [gn build] (manually) merge 2124ca1d5 2020-09-19 08:29:55 -04:00