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Commit Graph

90843 Commits

Author SHA1 Message Date
Akira Hatanaka
33684b1e2e [mips] Add mips-specific nodes which will be used to select multiply and divide
instructions.

llvm-svn: 178394
2013-03-30 01:14:04 +00:00
Akira Hatanaka
aa7cae6b45 [mips] Implement getRepRegClassFor in MipsSETargetLowering. This function is
called in several places in ScheduleDAGRRList.cpp.

llvm-svn: 178393
2013-03-30 01:12:05 +00:00
Akira Hatanaka
438e940329 [mips] Fix MipsSEInstrInfo::copyPhysReg, loadRegFromStack and storeRegToStack
to handle accumulator registers.

llvm-svn: 178392
2013-03-30 01:08:05 +00:00
Akira Hatanaka
51b8645403 [mips] Expand pseudo load, store and copy instructions right before
callee-saved scan.

The code makes use of register's scavenger's capability to spill multiple
registers.

llvm-svn: 178391
2013-03-30 01:04:11 +00:00
Akira Hatanaka
86302e607d [mips] Define pseudo instructions for spilling and copying accumulator
registers.

llvm-svn: 178390
2013-03-30 00:54:52 +00:00
Eric Christopher
05df599ea8 Use SmallVectorImpl instead of SmallVector at the uses.
llvm-svn: 178386
2013-03-29 23:34:06 +00:00
Bob Wilson
7e366d2845 Run the ObjCARCContract pass for LTO. <rdar://problem/13538084>
llvm-svn: 178385
2013-03-29 23:28:55 +00:00
Michael Gottesman
1bc2d353ed Updated test0 of retain-not-declared.ll to reflect the fact that objc-arc-expand runs before objc-arc/objc-arc-contract.
Specifically, objc-arc-expand will make sure that the
objc_retainAutoreleasedReturnValue, objc_autoreleaseReturnValue, and ret
will all have %call as an argument.

llvm-svn: 178382
2013-03-29 22:44:59 +00:00
Jean-Luc Duprat
7776961622 SmallVector and SmallPtrSet allocations now power-of-two aligned.
This time tested on both OSX and Linux.

llvm-svn: 178377
2013-03-29 22:07:12 +00:00
Sean Silva
04c7342f29 [docs] The STL "binary search" has a non-obvious name.
std::lower_bound is the canonical "binary search" in the STL
(std::binary_search generally is not what you want). The name actually
makes a lot of sense (and also has a beautiful symmetry with the
std::upper_bound algorithm). The name is nonetheless non-obvious.

Also, remove mention of "radix search". It's not even clear how that
would work in the context of a sorted vector. AFAIK "radix search" only
makes sense when you have a trie-like data structure.

llvm-svn: 178376
2013-03-29 21:57:47 +00:00
Timur Iskhodzhanov
d7d35221f7 Exclude the X86/complex-fca.ll test at it probably wasn't supposed to work on Windows
llvm-svn: 178375
2013-03-29 21:54:00 +00:00
Michael Gottesman
c7ef28e19f Add clang.arc.used to ModuleHasARC so ARC always runs if said call is present in a module.
clang.arc.used is an interesting call for ARC since ObjCARCContract
needs to run to remove said intrinsic to avoid a linker error (since the
call does not exist).

llvm-svn: 178369
2013-03-29 21:15:23 +00:00
Jyotsna Verma
91f1858936 Hexagon: Add emitFrameIndexDebugValue function to emit debug information.
llvm-svn: 178368
2013-03-29 21:09:53 +00:00
Eric Christopher
cd1e668cce Use 12 as the magic number for our abbreviation data and our
die values. A lot of DIEs have 10 attributes in C++ code (example
clang), none had more than 12. Seems like a good default.

llvm-svn: 178366
2013-03-29 20:23:06 +00:00
Eric Christopher
4658dc0478 Move the construction of the skeleton compile unit after the
entire original compile unit has been constructed.

llvm-svn: 178365
2013-03-29 20:23:02 +00:00
Adrian Prantl
dd8a6dc41a move testcase into appropriate X86 subdirectory.
llvm-svn: 178364
2013-03-29 20:14:08 +00:00
Hal Finkel
c14a74d243 Implement FRINT lowering on PPC using frin
Like nearbyint, rint can be implemented on PPC using the frin instruction. The
complication comes from the fact that rint needs to set the FE_INEXACT flag
when the result does not equal the input value (and frin does not do that). As
a result, we use a custom inserter which, after the rounding, compares the
rounded value with the original, and if they differ, explicitly sets the XX bit
in the FPSCR register (which corresponds to FE_INEXACT).

Once LLVM has better modeling of the floating-point environment we should be
able to (often) eliminate this extra complexity.

llvm-svn: 178362
2013-03-29 19:41:55 +00:00
Akira Hatanaka
251bd9f852 [mips] Define a function which returns the GPR register class.
llvm-svn: 178359
2013-03-29 19:17:42 +00:00
Andrew Trick
4e1ed3a6dc Fix TableGen subtarget-emitter to handle A9/Swift.
A9 uses itinerary classes, Swift uses RW lists. This tripped some
verification when we're expanding variants. I had to refine the
verification a bit.

llvm-svn: 178357
2013-03-29 19:08:31 +00:00
Matt Arsenault
fe0553b737 Build fixes for STLPort + GCC
llvm-svn: 178356
2013-03-29 18:48:45 +00:00
Matt Arsenault
ec92115e0d Fix loop style
llvm-svn: 178355
2013-03-29 18:48:42 +00:00
Adrian Prantl
324e4868cb Split the llvm/tools/clang/test/CodeGenObjC/debug-info-blocks.m testcase into a CFE and LLVM part.
rdar://problem/12767564

llvm-svn: 178353
2013-03-29 18:08:14 +00:00
Benjamin Kramer
279e5cfa9a Remove the old CodePlacementOpt pass.
It was superseded by MachineBlockPlacement and disabled by default since LLVM 3.1.

llvm-svn: 178349
2013-03-29 17:14:24 +00:00
Nadav Rotem
6d5518d53d Fix a typo
llvm-svn: 178346
2013-03-29 16:34:23 +00:00
Jyotsna Verma
c91629764d Hexagon: Disable DwarfUsesInlineInfoSection flag.
llvm-svn: 178345
2013-03-29 15:46:12 +00:00
Hal Finkel
3493fd8e51 Add PPC FP rounding instructions fri[mnpz]
These instructions are available on the P5x (and later) and on the A2. They
implement the standard floating-point rounding operations (floor, trunc, etc.).
One caveat: frin (round to nearest) does not implement "ties to even", and so
is only enabled in fast-math mode.

llvm-svn: 178337
2013-03-29 08:57:48 +00:00
Rafael Espindola
e78555387c Revert "Fix allocations of SmallVector and SmallPtrSet so they are more prone to"
This reverts commit 617330909f0c26a3f2ab8601a029b9bdca48aa61.

It broke the bots:

/home/clangbuild2/clang-ppc64-2/llvm.src/unittests/ADT/SmallVectorTest.cpp:150: PushPopTest
/home/clangbuild2/clang-ppc64-2/llvm.src/unittests/ADT/SmallVectorTest.cpp:118: Failure
Value of: v[i].getValue()
  Actual: 0
Expected: value
Which is: 2

llvm-svn: 178334
2013-03-29 07:11:21 +00:00
Jean-Luc Duprat
0ba254f23f Fix allocations of SmallVector and SmallPtrSet so they are more prone to
being power-of-two sized.

llvm-svn: 178332
2013-03-29 05:45:22 +00:00
Michael Gottesman
6eceba6dde Removed trailing whitespace.
llvm-svn: 178329
2013-03-29 05:13:07 +00:00
Akira Hatanaka
b8d0cfec7c [mips] Change type of accumulator registers to Untyped. Add two more accumulator
register classes for Mips64 and DSP-ASE.

No functionality changes.

llvm-svn: 178328
2013-03-29 03:27:21 +00:00
Akira Hatanaka
fe61de70c1 [mips] Define overloaded versions of storeRegToStack and loadRegFromStack.
No functionality changes.

llvm-svn: 178327
2013-03-29 02:14:12 +00:00
Akira Hatanaka
c27c81aa86 [mips] Add parameter Alignment to MipsFrameLowering's constructor.
No functionality changes.

llvm-svn: 178326
2013-03-29 01:51:04 +00:00
Dan Gohman
333b99112b Revert r178166. According to Howard, this code is actually ok.
llvm-svn: 178319
2013-03-29 00:13:08 +00:00
Jack Carter
ab230573a8 [Mips Assembler] Add support for OR macro with imediate opperand
Mips assembler supports macros that allows the OR instruction 
to have an immediate parameter. This patch adds an instruction 
alias that converts this macro into a Mips ORI instruction. 

Contributer: Vladimir Medic
llvm-svn: 178316
2013-03-28 23:45:13 +00:00
Michael Liao
427149cbcf Add support of RDSEED defined in AVX2 extension
llvm-svn: 178314
2013-03-28 23:41:26 +00:00
Michael Liao
aec693ab31 Enhance boolean simplification to handle 16-/64-bit RDRAND
- RDRAND always clears the destination value when a random value is not
  available (i.e. CF == 0). This value is truncated or zero-extended as
  the false boolean value to be returned. Boolean simplification needs
  to skip this 'zext' or 'trunc' node.

llvm-svn: 178312
2013-03-28 23:38:52 +00:00
Michael Liao
d961d7a7b3 Skip moving call address loading into callseq when targets prefer register indirect call.
To enable a load of a call address to be folded with that call, this
load is moved from outside of callseq into callseq. Such a moving
adds a non-glued node (that load) into a glued sequence. This non-glue
load is only removed when DAG selection folds them into a memory form
call instruction. When such instruction selection is disabled, it breaks
DAG schedule.

To prevent that, such moving is disabled when target favors register
indirect call.

Previous workaround disabling CALL32m/CALL64m insn selection is removed.

llvm-svn: 178308
2013-03-28 23:13:21 +00:00
Michael Gottesman
455f4aa991 Removed dead code from ObjCARCOpts relating to tracking objc_retainBlocks through the ARC Dataflow analysis. By the time we get to the ARC dataflow analysis, any objc_retainBlock calls are not optimizable.
llvm-svn: 178306
2013-03-28 23:08:44 +00:00
Chad Rosier
5668c6b7c7 [fast-isel] Add a preemptive fix for the case where we fail to materialize an
immediate in a register.  I don't believe this should ever fail, but I see no
harm in trying to make this code bullet proof.

I've added an assert to ensure my assumtion is correct.  If the assertion fires
something is wrong and we should fix it, rather then just silently fall back to
SelectionDAG isel.

llvm-svn: 178305
2013-03-28 23:04:47 +00:00
Jack Carter
1e744ec264 [Mips Assembler] Add alias definitions for jal
Mips assembler allows following to be used as aliased instructions:
jal $rs for jalr $rs
jal $rd,$rd for jalr $rd,$rs

This patch provides alias definitions in td files and test cases to show the usage.

Contributer: Vladimir Medic
llvm-svn: 178304
2013-03-28 23:02:21 +00:00
Nadav Rotem
705ec0e7e3 Add the X86 FMAs to the scheduling model.
llvm-svn: 178303
2013-03-28 22:54:45 +00:00
Bill Wendling
9c95fdda8f Minor simplification.
Go ahead and use the full path for both the .gcno and .gcda files.

llvm-svn: 178302
2013-03-28 22:40:08 +00:00
Nadav Rotem
401bba05fe Add the Haswell machine model.
llvm-svn: 178301
2013-03-28 22:34:46 +00:00
Nadav Rotem
e5f49b65f6 Remove the unused port from the SandyBridge machine model
llvm-svn: 178300
2013-03-28 22:32:41 +00:00
Michael Liao
30577169a4 Add ADX CPUID detection
llvm-svn: 178299
2013-03-28 22:29:53 +00:00
Eric Christopher
43672e076b These two are default in the constructor for MCAsmInfo.
llvm-svn: 178293
2013-03-28 21:37:18 +00:00
Timur Iskhodzhanov
d7de83d51c Make Win32 put the SRet address into EAX, fixes PR15556
llvm-svn: 178291
2013-03-28 21:30:04 +00:00
Hal Finkel
8672bd7c2a Specify CPUs on the PPC bswap-load-store test
Otherwise, the CHECK-NOT's might trigger depending on the host's CPU.

llvm-svn: 178287
2013-03-28 20:35:18 +00:00
Hal Finkel
88670ad5f4 Only enable 64-bit bswap DAG combines for PPC64
Compiling in 32-bit mode on a P7 would assert after 64-bit DAG combines were
added for bswap with load/store. This is because these combines are really only
valid in 64-bit mode, regardless of the CPU (and this was not being checked).

llvm-svn: 178286
2013-03-28 20:23:46 +00:00
Michael Gottesman
08570554c2 Non optimizable objc_retainBlock calls are not forwarding.
Since we handle optimizable objc_retainBlocks through strength reduction
in OptimizableIndividualCalls, we know that all code after that point
will only see non-optimizable objc_retainBlock calls. IsForwarding is
only called by functions after that point, so it is ok to just classify
objc_retainBlock as non-forwarding.

<rdar://problem/13249661>.

llvm-svn: 178285
2013-03-28 20:11:30 +00:00