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Commit Graph

128 Commits

Author SHA1 Message Date
Chris Lattner
9ceee53f9a Emit this:
static const TargetOperandInfo OperandInfo6[] = { { &PPC32::CRRCRegClass }, { 0 }, };

instead of this:

static const TargetOperandInfo OperandInfo6[] = { { PPC32::CRRCRegisterClass }, { 0 }, };

For operand information, which does not require dynamic (startup-time)
initialization.

llvm-svn: 22931
2005-08-19 20:29:14 +00:00
Chris Lattner
916e016ac1 Expose the derived register classes to the public header, allowing them
to be accessed.

llvm-svn: 22930
2005-08-19 20:23:42 +00:00
Chris Lattner
20c1c4cf07 Split register class "Methods" into MethodProtos and MethodBodies
llvm-svn: 22928
2005-08-19 19:12:51 +00:00
Chris Lattner
cef54bfd28 Refactor to use Target.getRegisterClasses consistently, which provides
anonymous regclass definition renaming.

Change the generated code to emit register classes as properly namespace
qualified entities like everything else.

expose the actual class definition as an object, though this isn't quite
usable yet.

llvm-svn: 22920
2005-08-19 18:47:59 +00:00
Chris Lattner
077a4e87c4 Emit real operand info for instructions. This currently works but is bad
in one way: the generated tables require dynamic initialization for the
register classes.  This will be fixed in a future patch.

llvm-svn: 22919
2005-08-19 18:46:26 +00:00
Chris Lattner
341308dc6b Read the namespace field from register classes
llvm-svn: 22918
2005-08-19 18:45:20 +00:00
Chris Lattner
bf7633b73b add a setName method to record
llvm-svn: 22912
2005-08-19 17:58:49 +00:00
Chris Lattner
1344e9cf9c Add a setName method to Record.
llvm-svn: 22911
2005-08-19 17:58:11 +00:00
Chris Lattner
36f99a1374 For now, just emit empty operand info structures.
llvm-svn: 22910
2005-08-19 16:57:28 +00:00
Chris Lattner
5ac318c67b Fix a problem jeffc noticed
llvm-svn: 22903
2005-08-19 06:16:04 +00:00
Chris Lattner
1685432a06 The code emitter generator only supports targets with 32-bit instruction
words.  There is no way for one of these targets to have a > 32-bit immediate!

llvm-svn: 22897
2005-08-19 01:04:33 +00:00
Chris Lattner
7ab998463c now that all of the targets are clean w.r.t. the number of operands for each
instruction defined, actually emit this to the InstrInfoDescriptor, which
allows an assert in the machineinstrbuilder to do some checking for us,
and is required by the dag->dag emitter

llvm-svn: 22895
2005-08-19 00:59:49 +00:00
Chris Lattner
d03fa09ce7 Figure out how many operands each instruction has, keep track of whether
or not it's variable.

llvm-svn: 22885
2005-08-18 23:38:41 +00:00
Chris Lattner
1f718aa8b5 revert this change, which causes breakage, temporarily
llvm-svn: 22880
2005-08-18 22:12:31 +00:00
Chris Lattner
b312f4d374 When emitting implicit use/def lists, only emit each unique list once. Though
LLVM is able to merge identical static const globals, GCC isn't, and this caused
some bloat in the generated data.  This has a marginal effect on PPC, shrinking
the implicit sets from 10->4, but shrinks X86 from 179 to 23, a much bigger
reduction.

This should speed up the register allocator as well by reducing the dcache
footprint for this static data.

llvm-svn: 22879
2005-08-18 21:36:47 +00:00
Chris Lattner
d3814ff064 Fill in the numOperands field of the TargetInstrDescriptor struct from the
.td file.

llvm-svn: 22873
2005-08-18 19:45:37 +00:00
Jeff Cohen
bd51ec7461 Eliminate all remaining tabs and trailing spaces.
llvm-svn: 22523
2005-07-27 06:12:32 +00:00
Chris Lattner
bee317e9b0 Fix PR595: These error messages should not be looking at CGI.Name, they
should be looking at CGI.TheDef->getName().

llvm-svn: 22445
2005-07-15 22:43:04 +00:00
Nate Begeman
c871411c9d Add support for a TODO; instructions in .td files can now have arguments
printed as part of the opcode.  This allows something like
cmp${cc}ss in the x86 backed to be printed as cmpltss, cmpless, etc.
depending on what the value of $cc is.

llvm-svn: 22439
2005-07-14 22:50:30 +00:00
Jeff Cohen
4d31aeb9df Eliminate tabs and trailing spaces
llvm-svn: 21441
2005-04-22 04:13:13 +00:00
Misha Brukman
960a8d47d7 Remove trailing whitespace
llvm-svn: 21428
2005-04-22 00:00:37 +00:00
Chris Lattner
070188a856 ignore generated files
llvm-svn: 21362
2005-04-19 15:34:36 +00:00
Chris Lattner
0c97ef0c04 fix bogus warning
llvm-svn: 21361
2005-04-19 15:32:30 +00:00
Chris Lattner
c2f7fcfbba Major change to tblgen: instead of resolving values every time a class is
finished up, only resolve fully when the def is defined.  This allows things
to be changed and all uses to be propagated through.  This implements
TableGen/LazyChange.td and fixes TemplateArgRename.td in the process.

None of the .td files used in LLVM backends are changed at all by this
patch.

llvm-svn: 21344
2005-04-19 03:36:21 +00:00
Chris Lattner
57b0bbfcbd implementing shifting of literal integers
llvm-svn: 21336
2005-04-19 01:17:35 +00:00
Chris Lattner
414d27b765 Add initial lexer and parser support for shifting values. Every use of this
will lead to it being rejected though.

llvm-svn: 21335
2005-04-19 01:11:03 +00:00
Chris Lattner
fb921a5722 Minor fix.
llvm-svn: 19761
2005-01-22 20:59:38 +00:00
Chris Lattner
078cda0bb3 This is the final big of factoring. This shares cases in suboperand
differences, which means that identical instructions (after stripping off
the first literal string) do not run any different code at all.  On the X86,
this turns this code:

    switch (MI->getOpcode()) {
    case X86::ADC32mi: printOperand(MI, 4, MVT::i32); break;
    case X86::ADC32mi8: printOperand(MI, 4, MVT::i8); break;
    case X86::ADC32mr: printOperand(MI, 4, MVT::i32); break;
    case X86::ADD32mi: printOperand(MI, 4, MVT::i32); break;
    case X86::ADD32mi8: printOperand(MI, 4, MVT::i8); break;
    case X86::ADD32mr: printOperand(MI, 4, MVT::i32); break;
    case X86::AND32mi: printOperand(MI, 4, MVT::i32); break;
    case X86::AND32mi8: printOperand(MI, 4, MVT::i8); break;
    case X86::AND32mr: printOperand(MI, 4, MVT::i32); break;
    case X86::CMP32mi: printOperand(MI, 4, MVT::i32); break;
    case X86::CMP32mr: printOperand(MI, 4, MVT::i32); break;
    case X86::MOV32mi: printOperand(MI, 4, MVT::i32); break;
    case X86::MOV32mr: printOperand(MI, 4, MVT::i32); break;
    case X86::OR32mi: printOperand(MI, 4, MVT::i32); break;
    case X86::OR32mi8: printOperand(MI, 4, MVT::i8); break;
    case X86::OR32mr: printOperand(MI, 4, MVT::i32); break;
    case X86::ROL32mi: printOperand(MI, 4, MVT::i8); break;
    case X86::ROR32mi: printOperand(MI, 4, MVT::i8); break;
    case X86::SAR32mi: printOperand(MI, 4, MVT::i8); break;
    case X86::SBB32mi: printOperand(MI, 4, MVT::i32); break;
    case X86::SBB32mi8: printOperand(MI, 4, MVT::i8); break;
    case X86::SBB32mr: printOperand(MI, 4, MVT::i32); break;
    case X86::SHL32mi: printOperand(MI, 4, MVT::i8); break;
    case X86::SHLD32mrCL: printOperand(MI, 4, MVT::i32); break;
    case X86::SHR32mi: printOperand(MI, 4, MVT::i8); break;
    case X86::SHRD32mrCL: printOperand(MI, 4, MVT::i32); break;
    case X86::SUB32mi: printOperand(MI, 4, MVT::i32); break;
    case X86::SUB32mi8: printOperand(MI, 4, MVT::i8); break;
    case X86::SUB32mr: printOperand(MI, 4, MVT::i32); break;
    case X86::TEST32mi: printOperand(MI, 4, MVT::i32); break;
    case X86::TEST32mr: printOperand(MI, 4, MVT::i32); break;
    case X86::TEST8mi: printOperand(MI, 4, MVT::i8); break;
    case X86::XCHG32mr: printOperand(MI, 4, MVT::i32); break;
    case X86::XOR32mi: printOperand(MI, 4, MVT::i32); break;
    case X86::XOR32mi8: printOperand(MI, 4, MVT::i8); break;
    case X86::XOR32mr: printOperand(MI, 4, MVT::i32); break;
    }

into this:

    switch (MI->getOpcode()) {
    case X86::ADC32mi:
    case X86::ADC32mr:
    case X86::ADD32mi:
    case X86::ADD32mr:
    case X86::AND32mi:
    case X86::AND32mr:
    case X86::CMP32mi:
    case X86::CMP32mr:
    case X86::MOV32mi:
    case X86::MOV32mr:
    case X86::OR32mi:
    case X86::OR32mr:
    case X86::SBB32mi:
    case X86::SBB32mr:
    case X86::SHLD32mrCL:
    case X86::SHRD32mrCL:
    case X86::SUB32mi:
    case X86::SUB32mr:
    case X86::TEST32mi:
    case X86::TEST32mr:
    case X86::XCHG32mr:
    case X86::XOR32mi:
    case X86::XOR32mr: printOperand(MI, 4, MVT::i32); break;
    case X86::ADC32mi8:
    case X86::ADD32mi8:
    case X86::AND32mi8:
    case X86::OR32mi8:
    case X86::ROL32mi:
    case X86::ROR32mi:
    case X86::SAR32mi:
    case X86::SBB32mi8:
    case X86::SHL32mi:
    case X86::SHR32mi:
    case X86::SUB32mi8:
    case X86::TEST8mi:
    case X86::XOR32mi8: printOperand(MI, 4, MVT::i8); break;
    }

After this, the generated asmwriters look pretty much as though they were
generated by hand.  This shrinks the X86 asmwriter.inc files from 55101->39669
and 55429->39551 bytes each, and PPC from 16766->12859 bytes.

llvm-svn: 19760
2005-01-22 20:31:17 +00:00
Chris Lattner
eee6c31449 Implement *even more* factoring. In particular, if all of the instruction
strings starts out with a constant string, we emit the string first, using
a table lookup (instead of a switch statement).

Because this is usually the opcode portion of the asm string, the differences
between the instructions have now been greatly reduced.  This allows many
more case statements to be grouped together.

This patch also allows instruction cases to be grouped together when the
instruction patterns are exactly identical (common after the opcode string
has been ripped off), and when the differing operand is a MachineInstr
operand that needs to be formatted.

The end result of this is a mean and lean generated AsmPrinter!

llvm-svn: 19759
2005-01-22 19:22:23 +00:00
Chris Lattner
f78580dcec Refactor code for numbering instructions into CodeGenTarget.
llvm-svn: 19758
2005-01-22 18:58:51 +00:00
Jeff Cohen
50c819634d Fix VC++ compilation error
llvm-svn: 19757
2005-01-22 18:50:10 +00:00
Chris Lattner
a030a47a51 Implement factoring of instruction pattern strings. In particular, instead of
emitting code like this:

  case PPC::ADD: O  << "add ";  printOperand(MI, 0, MVT::i64); O  << ", ";  prin
tOperand(MI, 1, MVT::i64); O  << ", ";  printOperand(MI, 2, MVT::i64); O  << '\n
'; break;
  case PPC::ADDC: O  << "addc ";  printOperand(MI, 0, MVT::i64); O  << ", ";  pr
intOperand(MI, 1, MVT::i64); O  << ", ";  printOperand(MI, 2, MVT::i64); O  << '
\n'; break;
  case PPC::ADDE: O  << "adde ";  printOperand(MI, 0, MVT::i64); O  << ", ";  pr
intOperand(MI, 1, MVT::i64); O  << ", ";  printOperand(MI, 2, MVT::i64); O  << '
\n'; break;
...

Emit code like this:

  case PPC::ADD:
  case PPC::ADDC:
  case PPC::ADDE:
  ...
    switch (MI->getOpcode()) {
    case PPC::ADD: O << "add "; break;
    case PPC::ADDC: O << "addc "; break;
    case PPC::ADDE: O << "adde "; break;
    ...
    }
    printOperand(MI, 0, MVT::i64);
    O << ", ";
    printOperand(MI, 1, MVT::i64);
    O << ", ";
    printOperand(MI, 2, MVT::i64);
    O << "\n";
    break;

This shrinks the PPC asm writer from 24785->15205 bytes (even though the new
asmwriter has much more whitespace than the old one), and the X86 printers shrink
quite a bit too.  The important implication of this is that GCC no longer hits swap
when building the PPC backend in optimized mode.  Thus this fixes PR448.

-Chris

llvm-svn: 19755
2005-01-22 18:38:13 +00:00
Chris Lattner
3e855b097c Fix the ::: problem
llvm-svn: 19754
2005-01-22 18:18:59 +00:00
Chris Lattner
cc09d8ac1e Minor refactoring, no functionality change.
llvm-svn: 19753
2005-01-22 17:40:38 +00:00
Chris Lattner
67cbd23ad5 Seperate asmstring parsing from emission. This allows the code to be simpler
and more understandable.  It also allows us to do simple things like fold
consequtive literal strings together.  For example, instead of emitting this
for the X86 backend:

  O  << "adc" << "l" << " ";

we now generate this:

  O << "adcl ";

*whoa* :)

This shrinks the X86 asmwriters from 62729->58267 and 65176->58644 bytes
for the intel/att asm writers respectively.

llvm-svn: 19749
2005-01-22 17:32:42 +00:00
Andrew Lenharth
e3d81200bc make double-dollar properly escape asmstrings
llvm-svn: 19740
2005-01-22 00:35:22 +00:00
Chris Lattner
2aef5783b0 Expose isConvertibleToThreeAddress and isCommutable bits to the code generator.
llvm-svn: 19243
2005-01-02 02:29:04 +00:00
Reid Spencer
7b0596782a For PR387:
Make this compile without warning when -Woverloaded-virtual is used.

llvm-svn: 18588
2004-12-06 23:42:37 +00:00
Reid Spencer
bbdeb2181d Fix usage of changed function prototype
llvm-svn: 17798
2004-11-14 22:30:54 +00:00
Chris Lattner
499e1b16a7 Quiet VC++ warnings
llvm-svn: 17484
2004-11-05 04:50:59 +00:00
Reid Spencer
acb1305e99 Internalize variable names to prevent recursive assignment. Cleanup docs.
llvm-svn: 17359
2004-10-30 09:19:36 +00:00
Reid Spencer
d3f7233495 Change Library Names Not To Conflict With Others When Installed
llvm-svn: 17286
2004-10-27 23:18:45 +00:00
Chris Lattner
dd0094e4ed Convert 'struct' to 'class' in various places to adhere to the coding standards
and work better with VC++.  Patch contributed by Morten Ofstad!

llvm-svn: 17281
2004-10-27 16:14:51 +00:00
Chris Lattner
0566f4f4ce Make VC happier, patch contributed by Morten Ofstad
llvm-svn: 17179
2004-10-23 04:58:50 +00:00
Reid Spencer
5574857063 We're not doing automake any more
llvm-svn: 17168
2004-10-22 21:02:23 +00:00
Reid Spencer
e48ba34fd4 We won't use automake
llvm-svn: 17155
2004-10-22 03:35:04 +00:00
Reid Spencer
ce514b1c2c Initial automake generated Makefile template
llvm-svn: 17136
2004-10-18 23:55:41 +00:00
Misha Brukman
4e252ebfa0 * Factor out (into new fn) a loop emitting operand shifts into the instruction
* Reverse instruction bit components for a LittleEndian-style encoding
* Fix some comments and spacing

llvm-svn: 16975
2004-10-14 05:53:01 +00:00
Misha Brukman
a87a2029e4 * Add option to read isLittleEndianEncoding for InstrInfo classes
* Doxygen-ify some function comments

llvm-svn: 16974
2004-10-14 05:50:43 +00:00
Chris Lattner
8dd656b17b Patch to make VS happier, thanks to Morten Ofstad for pointing this out.
llvm-svn: 16956
2004-10-13 15:25:46 +00:00