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53 Commits

Author SHA1 Message Date
Duraid Madina
d2ae9221c7 assorted fixes: 
* clean up immediates (we use 14, 22 and 64 bit immediates now. sane.)
  * fold r0/f0/f1 registers into comparisons against 0/0.0/1.0
  * fix nasty thinko - didn't use two-address form of conditional add
    for extending bools to integers, so occasionally there would be
    garbage in the result. it's amazing how often zeros are just
    sitting around in registers ;) - this should fix a bunch of tests.

llvm-svn: 21221
 2005-04-11 05:55:56 +00:00
Duraid Madina
03efd3bea9 daintyness 
llvm-svn: 20955
 2005-03-31 07:36:43 +00:00
Duraid Madina
79022e1b87 and so it begins... 
PHASE 1: write instruction selector
PHASE 2: ???
PHASE 3: profit!

llvm-svn: 20652
 2005-03-17 18:17:03 +00:00