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Commit Graph

181665 Commits

Author SHA1 Message Date
Simon Pilgrim
f595a46554 [DAGCombine] visitINSERT_SUBVECTOR - use uint64_t subvector index. NFCI.
Keep the uint64_t type from getZExtValue() to stop truncation/extension overflow warnings in MSVC in subvector index math.

llvm-svn: 365621
2019-07-10 12:21:35 +00:00
Simon Pilgrim
d25f434c37 [X86] EltsFromConsecutiveLoads - store Loads on a per-element basis. NFCI.
Cache the LoadSDNode nodes so we can easily map to/from the element index instead of packing them together - this will be useful for future patches for PR16739 etc.

llvm-svn: 365620
2019-07-10 11:26:57 +00:00
Nikola Prica
5d3276d477 [ELF] Loose a condition for relocation with a symbol
Deleted code was introduced as a work around for a bug in the gold linker
(http://sourceware.org/PR16794). Test case that was given as a reason for
this part of code, the one on previous link, now works for the gold.
This condition is too strict and when a code is compiled with debug info
it forces generation of numerous relocations with symbol for architectures
that do not have relocation addend.

Reviewers: arsenm, espindola

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D64327

llvm-svn: 365618
2019-07-10 11:17:48 +00:00
Simon Pilgrim
a518db5b17 [X86][SSE] EltsFromConsecutiveLoads - add basic dereferenceable support
This patch checks to see if the vector element loads are based off a dereferenceable pointer that covers the entire vector width, in which case we don't need to have element loads at both extremes of the vector width - just the start (base pointer) of it.

Another step towards partial vector loads......

Differential Revision: https://reviews.llvm.org/D64205

llvm-svn: 365614
2019-07-10 10:46:36 +00:00
Simon Pilgrim
28c7a0866c Fix const/non-const lambda return type warning. NFCI.
llvm-svn: 365613
2019-07-10 10:45:09 +00:00
Simon Pilgrim
630814759f Fix "result of 32-bit shift implicitly converted to 64 bits" warning. NFCI.
llvm-svn: 365612
2019-07-10 10:34:44 +00:00
Serguei Katkov
96f7f32d3a [SimpleLoopUnswitch] Don't consider unswitching switch insructions with one unique successor
Only instructions with two or more unique successors should be considered for unswitching.

Patch Author: Daniil Suchkov.

Reviewers: reames, asbirlea, skatkov
Reviewed By: skatkov
Subscribers: hiraditya, llvm-commits
Differential Revision: https://reviews.llvm.org/D64404

llvm-svn: 365611
2019-07-10 10:25:22 +00:00
Mikhail Maltsev
b098408d2a [ARM] Enable VPUSH/VPOP aliases when either MVE or VFP is present
Summary:
Use the same predicates as VSTMDB/VLDMIA since VPUSH/VPOP alias to
these.

Patch by Momchil Velikov.

Reviewers: ostannard, simon_tatham, SjoerdMeijer, samparker, t.p.northover, dmgreen

Reviewed By: dmgreen

Subscribers: javed.absar, kristof.beyls, hiraditya, dmgreen, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64413

llvm-svn: 365604
2019-07-10 08:59:17 +00:00
James Henderson
28db65394b [docs][llvm-dwarfdump] Normalise some wording
llvm-svn: 365603
2019-07-10 08:56:13 +00:00
George Rimar
6dff12ccb5 [test/Object/nm-trivial-object.test] - Remove 4 precompiled binaries.
This converts 5 precompiled binaries to YAMLs,
removes 4 from inputs and performs a cleanup.

Differential revision: https://reviews.llvm.org/D64246

llvm-svn: 365601
2019-07-10 08:40:11 +00:00
Serguei Katkov
8d2d364b6b [SimpleLoopUnswitch] Add a test case exposing a bug
This test exposes a bug in SimpleLoopUnswitch that leads to a crash on
assert(SuccessorsCount > 1 && "Cannot unswitch a condition without multiple distinct successors!");
when SimpleLoopUnswitch considers unswitching of a loop by a switch with one successor.

Fix will be submitted soon.

Patch Author: Daniil Suchkov.

Reviewers: reames, asbirlea, skatkov
Reviewed By: skatkov
Subscribers: zzheng, llvm-commits
Differential Revision: https://reviews.llvm.org/D64403

llvm-svn: 365600
2019-07-10 08:25:48 +00:00
Mikael Holmen
49b206f6c9 Silence gcc warning by adding parentheses to condition [NFC]
Without this gcc 7.4.0 complains with

  ../include/llvm/CodeGen/GlobalISel/LegalizationArtifactCombiner.h:457:54: error: suggest parentheses around '&&' within '||' [-Werror=parentheses]
                    isArtifactCast(TmpDef->getOpcode()) &&
                    ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~
                        "Expecting copy or artifact cast here");
                        ~

llvm-svn: 365597
2019-07-10 06:18:03 +00:00
Kristina Brooks
4fbce3ed85 Fix modular build issues caused by BitCodes.h
Consolidate llvm::BWH_* statics into an enum to fix
module build issues. This fixes the LLVM_Bitcode module,
getting rid of -Wmodules-ambiguous-internal-linkage.

Differential Revision: https://reviews.llvm.org/D64469

llvm-svn: 365594
2019-07-10 03:52:31 +00:00
Craig Topper
2b9b7605cb [X86] Limit getTargetConstantFromNode to only work on NormalLoads not extending loads.
This seems to fix a failure reported by Jordan Rupprecht, but we
don't have a reduced test case yet.

llvm-svn: 365589
2019-07-10 00:40:01 +00:00
Reid Kleckner
12eb282f10 [Support] Move llvm::MemoryBuffer to sys::fs::file_t
Summary:
On Windows, Posix integer file descriptors are a compatibility layer
over native file handles provided by the C runtime. There is a hard
limit on the maximum number of file descriptors that a process can open,
and the limit is 8192. LLD typically doesn't run into this limit because
it opens input files, maps them into memory, and then immediately closes
the file descriptor. This prevents it from running out of FDs.

For various reasons, I'd like to open handles to every input file and
keep them open during linking. That requires migrating MemoryBuffer over
to taking open native file handles instead of integer FDs.

Reviewers: aganea, Bigcheese

Reviewed By: aganea

Subscribers: smeenai, silvas, mehdi_amini, hiraditya, steven_wu, dexonsmith, dang, llvm-commits, zturner

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63453

llvm-svn: 365588
2019-07-10 00:34:13 +00:00
Tom Stellard
9440389bdd AMDGPU/GlobalISel: Add support for wide loads >= 256-bits
Summary:
This adds support for the most commonly used wide load types:
<8xi32>, <16xi32>, <4xi64>, and <8xi64>

Reviewers: arsenm

Reviewed By: arsenm

Subscribers: hiraditya, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, dstuttard, tpr, t-tye, volkan, Petar.Avramovic, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D57399

llvm-svn: 365586
2019-07-10 00:22:41 +00:00
Matt Arsenault
614009e347 GlobalISel: Implement lower for G_FCOPYSIGN
In SelectionDAG AMDGPU treated these as legal, but this was mostly
because the bitcasts required for FP types were painful. Theoretically
the bitpattern should eventually match to bfi, so don't bother trying
to get the patterns to import.

llvm-svn: 365583
2019-07-09 23:34:29 +00:00
Francis Visoiu Mistrih
a8a505adbc [Bitcode] Explicitly include Bitstream/BitCodes.h and BitstreamWriter.h
This fixes a modules issue.

llvm-svn: 365580
2019-07-09 23:20:01 +00:00
Francis Visoiu Mistrih
e890ba3771 [docs][Remarks] Add documentation for remarks in LLVM
This adds documentation that describes remarks in LLVM.

It aims at explaining what remarks are, how to enable them, and what
users can do with the different modes.

It lists all the available flags in LLVM (excluding clang), and
describes the expected YAML structure as well as the tools that support
the YAML format today.

Differential Revision: https://reviews.llvm.org/D64355

llvm-svn: 365578
2019-07-09 23:16:59 +00:00
Craig Topper
684dde9f6f [X86] Don't form extloads in combineExtInVec unless the load extension is legal.
This should prevent doing this on pre-sse4.1 targets or for 256
bit vectors without avx2.

I don't know of a failure from this. Op legalization will probably
take care of, but seemed better to be safe.

llvm-svn: 365577
2019-07-09 23:05:54 +00:00
Matt Arsenault
b54e55aa35 AMDGPU/GlobalISel: Fix legality for G_BUILD_VECTOR
llvm-svn: 365575
2019-07-09 22:48:04 +00:00
Stanislav Mekhanoshin
8d40d0cade [AMDGPU] gfx908 v_pk_fmac_f16 support
Differential Revision: https://reviews.llvm.org/D64433

llvm-svn: 365573
2019-07-09 22:42:24 +00:00
Peter Collingbourne
669d4d285e gn build: Merge r365536.
llvm-svn: 365572
2019-07-09 22:37:51 +00:00
Peter Collingbourne
d7ef3344f6 gn build: Merge r365532.
llvm-svn: 365571
2019-07-09 22:37:41 +00:00
Peter Collingbourne
5068264988 gn build: Merge r365541.
llvm-svn: 365570
2019-07-09 22:37:25 +00:00
Peter Collingbourne
08d71eb91b gn build: Merge r365531.
llvm-svn: 365569
2019-07-09 22:37:09 +00:00
Pavel Labath
a47c768731 Add lldb type unit support to the release notes
Reviewers: JDevlieghere, teemperor

Subscribers: llvm-commits, lldb-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64366

llvm-svn: 365568
2019-07-09 22:36:43 +00:00
Matt Arsenault
613605d1b3 GlobalISel: Combine unmerge of merge with intermediate cast
This eliminates some illegal intermediate vectors when operations are
scalarized.

llvm-svn: 365566
2019-07-09 22:19:13 +00:00
Vedant Kumar
9fc7728a1f [Profile] Support raw/indexed profiles larger than 4GB
rdar://45955976

llvm-svn: 365565
2019-07-09 22:01:04 +00:00
Yuanfang Chen
a9d665ebb5 [llvm-objdump] Keep warning for --disassemble-functions in correct order.
relative to normal output when dumping archive files.

prepare for PR35351.

Reviewers: jhenderson, grimar, MaskRay, rupprecht

Reviewed by: MaskRay, jhenderson

Differential Revision: https://reviews.llvm.org/D64165

llvm-svn: 365564
2019-07-09 21:53:33 +00:00
Stanislav Mekhanoshin
d5b428060d [AMDGPU] gfx908 mAI instructions, MC part
Differential Revision: https://reviews.llvm.org/D64446

llvm-svn: 365563
2019-07-09 21:43:09 +00:00
Nikita Popov
d88ac25674 [SLP] Optimize getSpillCost(); NFCI
For a given set of live values, the spill cost will always be the
same for each call. Compute the cost once and multiply it by the
number of calls.

(I'm not sure this spill cost modeling makes sense if there are
multiple calls, as the spill cost will likely be shared across
calls in that case. But that's how it currently works.)

llvm-svn: 365552
2019-07-09 20:24:44 +00:00
Peter Collingbourne
cdc1df0c0c hwasan: Improve precision of checks using short granule tags.
A short granule is a granule of size between 1 and `TG-1` bytes. The size
of a short granule is stored at the location in shadow memory where the
granule's tag is normally stored, while the granule's actual tag is stored
in the last byte of the granule. This means that in order to verify that a
pointer tag matches a memory tag, HWASAN must check for two possibilities:

* the pointer tag is equal to the memory tag in shadow memory, or
* the shadow memory tag is actually a short granule size, the value being loaded
  is in bounds of the granule and the pointer tag is equal to the last byte of
  the granule.

Pointer tags between 1 to `TG-1` are possible and are as likely as any other
tag. This means that these tags in memory have two interpretations: the full
tag interpretation (where the pointer tag is between 1 and `TG-1` and the
last byte of the granule is ordinary data) and the short tag interpretation
(where the pointer tag is stored in the granule).

When HWASAN detects an error near a memory tag between 1 and `TG-1`, it
will show both the memory tag and the last byte of the granule. Currently,
it is up to the user to disambiguate the two possibilities.

Because this functionality obsoletes the right aligned heap feature of
the HWASAN memory allocator (and because we can no longer easily test
it), the feature is removed.

Also update the documentation to cover both short granule tags and
outlined checks.

Differential Revision: https://reviews.llvm.org/D63908

llvm-svn: 365551
2019-07-09 20:22:36 +00:00
Philip Reames
b925e6ebac [PoisonChecking] Flesh out complete todo list for full coverage
Note: I don't actually plan to implement all of the cases at the moment, I'm just documenting them for completeness.  There's a couple of cases left which are practically useful for me in debugging loop transforms, and I'll probably stop there for the moment.
llvm-svn: 365550
2019-07-09 19:59:39 +00:00
Craig Topper
e048611781 [X86][AMDGPU][DAGCombiner] Move call to allowsMemoryAccess into isLoadBitCastBeneficial/isStoreBitCastBeneficial to allow X86 to bypass it
Basically the problem is that X86 doesn't set the Fast flag from
allowsMemoryAccess on certain CPUs due to slow unaligned memory
subtarget features. This prevents bitcasts from being folded into
loads and stores. But all vector loads and stores of the same width
are the same cost on X86.

This patch merges the allowsMemoryAccess call into isLoadBitCastBeneficial to allow X86 to skip it.

Differential Revision: https://reviews.llvm.org/D64295

llvm-svn: 365549
2019-07-09 19:55:28 +00:00
Reid Kleckner
2ac6ac4829 Fix build error for VC STL, use llvm::make_unique
llvm-svn: 365548
2019-07-09 19:51:58 +00:00
Stanislav Mekhanoshin
ee40ff6f51 [AMDGPU] gfx908 register file changes
Differential Revision: https://reviews.llvm.org/D64438

llvm-svn: 365546
2019-07-09 19:41:51 +00:00
Philip Reames
d64a701ab4 [PoisonCheker] Support for out of bounds operands on shifts + insert/extractelement
These are sources of poison which don't come from flags, but are clearly documented in the LangRef.  Left off support for scalable vectors for the moment, but should be easy to add if anyone is interested.  

llvm-svn: 365543
2019-07-09 19:26:12 +00:00
Sean Fertile
64a23513ff Boilerplate for producing XCOFF object files from the PowerPC backend.
Stubs out a number of the classes needed to produce a new object file format
(XCOFF) for the powerpc-aix target. For testing input is an empty module which
produces an object file with just a file header.

Differential Revision: https://reviews.llvm.org/D61694

llvm-svn: 365541
2019-07-09 19:21:01 +00:00
Simon Pilgrim
f3124bc7aa [X86] LowerToHorizontalOp - use count_if to count non-UNDEF ops. NFCI.
llvm-svn: 365540
2019-07-09 19:19:17 +00:00
Philip Reames
b7e737435c [PoisonChecking] Add validation rules for "exact" on sdiv/udiv
As directly stated in the LangRef, no ambiguity here...

llvm-svn: 365538
2019-07-09 18:56:41 +00:00
Bob Haarman
f4fcc00e4d [ThinLTO] only emit used or referenced CFI records to index
Summary: We emit CFI_FUNCTION_DEFS and CFI_FUNCTION_DECLS to
distributed ThinLTO indices to implement indirect function call
checking.  This change causes us to only emit entries for functions
that are either defined or used by the module we're writing the index
for (instead of all functions in the combined index), which can make
the indices substantially smaller.

Fixes PR42378.

Reviewers: pcc, vitalybuka, eugenis

Subscribers: mehdi_amini, hiraditya, dexonsmith, arphaman, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63887

llvm-svn: 365537
2019-07-09 18:50:55 +00:00
Philip Reames
8fea1df72a Add a transform pass to make the executable semantics of poison explicit in the IR
Implements a transform pass which instruments IR such that poison semantics are made explicit. That is, it provides a (possibly partial) executable semantics for every instruction w.r.t. poison as specified in the LLVM LangRef. There are obvious parallels to the sanitizer tools, but this pass is focused purely on the semantics of LLVM IR, not any particular source language.

The target audience for this tool is developers working on or targetting LLVM from a frontend. The idea is to be able to take arbitrary IR (with the assumption of known inputs), and evaluate it concretely after having made poison semantics explicit to detect cases where either a) the original code executes UB, or b) a transform pass introduces UB which didn't exist in the original program.

At the moment, this is mostly the framework and still needs to be fleshed out. By reusing existing code we have decent coverage, but there's a lot of cases not yet handled. What's here is good enough to handle interesting cases though; for instance, one of the recent LFTR bugs involved UB being triggered by integer induction variables with nsw/nuw flags would be reported by the current code.

(See comment in PoisonChecking.cpp for full explanation and context)

Differential Revision: https://reviews.llvm.org/D64215

llvm-svn: 365536
2019-07-09 18:49:29 +00:00
Sean Fertile
c0135f7359 Try to appease the Windows build bots.
Several of the conditonal operators commited in llvm-svn: 365524 fail to compile
on the windows buildbots. Converting to an if and early return to try to fix.

llvm-svn: 365535
2019-07-09 18:44:28 +00:00
Yonghong Song
714132b986 [BPF] Fix a typo in the file name
Fixed the file name from BPFAbstrctMemberAccess.cpp to
BPFAbstractMemberAccess.cpp.

Signed-off-by: Yonghong Song <yhs@fb.com>
llvm-svn: 365532
2019-07-09 18:35:46 +00:00
Peter Collingbourne
104bdbcb6c gn build: Merge r365503.
llvm-svn: 365530
2019-07-09 18:30:38 +00:00
Michael Liao
9bfa59ec99 [unittest] Add the missing bogus machine register info initialization.
llvm-svn: 365529
2019-07-09 18:22:48 +00:00
Stanislav Mekhanoshin
a7f5d761c5 [AMDGPU] gfx908 target
Differential Revision: https://reviews.llvm.org/D64429

llvm-svn: 365525
2019-07-09 18:10:06 +00:00
Sean Fertile
aa1c5e5087 [Object][XCOFF] Add support for 64-bit file header and section header dumping.
Adds a readobj dumper for 32-bit and 64-bit section header tables, and extend
support for the file-header dumping to include 64-bit object files. Also
refactors the binary file parsing to be done in a helper function in an attempt
to cleanup error handeling.

Differential Revision: https://reviews.llvm.org/D63843

llvm-svn: 365524
2019-07-09 18:09:11 +00:00
Sanjay Patel
7ca6dd8656 [InstCombine] add tests for trunc(load); NFC
I'm not sure if transforming any of these is valid as
a target-independent fold, but we might as well have
a few tests here to confirm or deny our position.

llvm-svn: 365523
2019-07-09 18:06:16 +00:00