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Commit Graph

181352 Commits

Author SHA1 Message Date
Konstantin Pyzhov
df53ea7203 [AMDGPU] Kernel arg metadata: added support for "__hip_texture" type.
Summary:
Hip texture type is equivalent to OpenCL image. So, we need to set the Image type for kernel arguments with __hip_texture type.

Differential revision: https://reviews.llvm.org/D63850

llvm-svn: 365073
2019-07-03 19:11:35 +00:00
Philip Reames
1d97c340ea [LFTR] Remove a stray variable shadow *of the same value* [NFC]
llvm-svn: 365072
2019-07-03 19:08:43 +00:00
Philip Reames
e44b7785ef [LFTR] Style and comment changes to clarify the narrow vs wide bitwidth evaluation behavior [NFC]
llvm-svn: 365071
2019-07-03 19:03:37 +00:00
Philip Reames
b00d273c24 [LFTR] Sink the decision not use truncate scheme for constants into genLoopLimit [NFC]
We might as well just evaluate the constants using SCEV, and having the cases grouped makes the logic slightly easier to read anyway.

llvm-svn: 365070
2019-07-03 18:41:03 +00:00
Jessica Paquette
1ad3046b4f Fix precedence in assert from r364961
Precedence was wrong in an assert added in r364961. Add braces around the
assertion condition to make it right.

See: https://reviews.llvm.org/D64084
llvm-svn: 365069
2019-07-03 18:30:01 +00:00
Philip Reames
516a32fa5d [LFTR] Remove falsely generalized (dead) code [NFC]
llvm-svn: 365067
2019-07-03 18:24:06 +00:00
Philip Reames
22a6f8f27d [LFTR] Hoist extend expressions outside of loops w/o waiting for LICM
The motivation for this is two fold:
1) Make the output (and thus tests)  a bit more readable to a human trying to understand the result of the transform
2) Reduce spurious diffs in a potential future change to restructure all of this logic to use SCEVExpander (which hoists by default)

llvm-svn: 365066
2019-07-03 18:18:36 +00:00
Alex Lorenz
da15aa4d0d [macCatalyst] Print out macCatalyst in llvm-objdump for the platform
'macCatalyst' is more readable than 'maccatalyst'.

llvm-svn: 365064
2019-07-03 17:46:30 +00:00
Jessica Paquette
31937cf55f [GlobalISel][AArch64] Use getConstantVRegValWithLookThrough for selectArithImmed
Instead of just stopping to see if we have a G_CONSTANT, instead, look through
G_TRUNCs, G_SEXTs, and G_ZEXTs.

This gives an average ~1.3% code size improvement on CINT2000 at -O3.

Differential Revision: https://reviews.llvm.org/D64108

llvm-svn: 365063
2019-07-03 17:46:23 +00:00
Robert Lougher
567aeabb96 [X86] Update test; NFC
This updates pr38743.ll after D62605.

llvm-svn: 365062
2019-07-03 17:45:24 +00:00
Robert Lougher
bc8c35fe89 [X86] Avoid SFB - Skip meta instructions
This patch generalizes the fix in D61680 to ignore all meta instructions,
not just debug info.

Patch by Chris Dawson.

Differential Revision: https://reviews.llvm.org/D62605

llvm-svn: 365061
2019-07-03 17:43:55 +00:00
Joel E. Denny
44dc561730 [Bitcode] Update CHECK-DAG usage in tests
This patch adjusts tests not to depend on deprecated FileCheck
behavior that permits overlapping matches within a block of
`CHECK-DAG` directives:

1. `thinlto-function-summary-originalnames.ll`: The directive with the
pattern `<COMBINED` is surely intended to match `<COMBINED ` (note the
trailing space), but it instead matches
`<COMBINED_GLOBALVAR_INIT_REFS`, for which there is a separate
directive.  With the deprecated behavior, both directives match the
latter text and neither match the former text.  I've adjusted the
former directive so it matches only the former text.

2. `thinlto-summary-local-5.0.ll`: Two directives have identical
patterns when they were clearly meant to have different patterns.

3. `upgrade-pointer-address-space.ll`: There are three identical
directives but only two occurrences of the matching text.  With the
deprecated behavior, they always match exactly the same text, so the
behavior can't have been useful.  I removed one of the directives and
converted the other two from `CHECK-DAG` to `CHECK`.

Reviewed By: probinson, aprantl

Differential Revision: https://reviews.llvm.org/D64036

llvm-svn: 365060
2019-07-03 17:31:43 +00:00
Francis Visoiu Mistrih
f0c4b59ebb [CodeGen] Make branch funnels pass the machine verifier
We previously marked all the tests with branch funnels as
`-verify-machineinstrs=0`.

This is an attempt to fix it.

1) `ICALL_BRANCH_FUNNEL` has no defs. Mark it as `let OutOperandList =
(outs)`

2) After that we hit an assert: ``` Assertion failed: (Op.getValueType()
!= MVT::Other && Op.getValueType() != MVT::Glue && "Chain and glue
operands should occur at end of operand list!"), function AddOperand,
file
/Users/francisvm/llvm/llvm/lib/CodeGen/SelectionDAG/InstrEmitter.cpp,
line 461.  ```

The chain operand was added at the beginning of the operand list. Move
that to the end.

3) After that we hit another verifier issue in the pseudo expansion
where the registers used in the cmps and jmps are not added to the
livein lists. Add the `EFLAGS` to all the new MBBs that we create.

PR39436

Differential Review: https://reviews.llvm.org/D54155

llvm-svn: 365058
2019-07-03 17:16:45 +00:00
Simon Pilgrim
22b3aa27a6 [X86] ComputeNumSignBitsForTargetNode - add target shuffle support.
llvm-svn: 365057
2019-07-03 17:06:59 +00:00
Roman Lebedev
df3ce19537 [NFC][InstCombine] onehot_merge.ll: add last few tests in the state they regress to in D62818
llvm-svn: 365056
2019-07-03 16:48:53 +00:00
Sanjay Patel
c04ead4c31 [SLP] add tests for bitcasted vector pointer load; NFC
I'm not sure if this falls within the scope of SLP,
but we could create vector loads for some of these
patterns.

llvm-svn: 365055
2019-07-03 16:46:14 +00:00
Amaury Sechet
43ae03fef5 Use getAllOnesConstants instead of -1 in DAGCombiner. NFC
llvm-svn: 365054
2019-07-03 16:34:36 +00:00
Philip Reames
2d847caee5 [SCEV] Preserve flags on add/muls in getSCEVATScope
We haven't changed the set of users, just specialized an operand for those users.  Given that, the previous wrap flags must still be correct.

Sorry for the lack of test case.  Noticed this while working on something else, and haven't figured out to exercise this standalone.

llvm-svn: 365053
2019-07-03 16:34:08 +00:00
Amaury Sechet
ece7389166 [DAGCombine] More diamong carry pattern optimization.
Summary:
This diff improve the capability of DAGCOmbine to generate linear carries propagation in presence of a diamond pattern. It is now able to match a large variety of different patterns rather than some hardcoded one.

Arguably, the codegen in test cases is not better, but this is to be expected. The goal of this transformation is more about canonicalisation than actual optimisation.

Reviewers: hfinkel, RKSimon, craig.topper

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D57302

llvm-svn: 365051
2019-07-03 16:15:59 +00:00
Simon Pilgrim
c473b8b6bd [X86][AVX] combineX86ShufflesRecursively - peek through extract_subvector
If we have more then 2 shuffle ops to combine, try to use combineX86ShuffleChainWithExtract to see if some are from the same super vector.

llvm-svn: 365050
2019-07-03 15:46:08 +00:00
Teresa Johnson
755dc0300b [ThinLTO] Fix gcc warnings from commit
Remove an unnecessary const from an Optional return type introduced
in r364960 that gcc 7.4.0 warns about. It is unnecessary and possibly
incorrect.

llvm-svn: 365047
2019-07-03 15:12:38 +00:00
Sam Parker
98e899e1ff [ARM] Fix for NDEBUG builds
Fix unused variable warning as well as a nonsense assert.

Differential Revision: https://reviews.llvm.org/D63816

llvm-svn: 365046
2019-07-03 14:39:23 +00:00
Simon Pilgrim
c1766168d9 [X86][AVX] Combine vpermi(bitcast(x)) -> bitcast(vpermi(x))
iff the number of elements doesn't change.

This gets around an issue with combineX86ShuffleChain not being able to hint which domain is preferred for shuffles that can be done with either.

Fixes regression introduced in rL365041

llvm-svn: 365044
2019-07-03 14:34:16 +00:00
James Molloy
8f41221e00 [SelectionDAG] Propagate alias metadata to target intrinsic nodes
When a target intrinsic has been determined to touch memory, we construct a MachineMemOperand during SDAG construction. In this case, we should propagate AAMDNodes metadata to the MachineMemOperand where available.

Differential revision: https://reviews.llvm.org/D64131

llvm-svn: 365043
2019-07-03 14:33:29 +00:00
James Henderson
56fa2402b4 [docs][llvm-objcopy] Write documentation for llvm-objcopy
This patch addresses https://bugs.llvm.org/show_bug.cgi?id=42183 by replacing
the stub markdown doc for llvm-objcopy with a full one describing the current
options available in llvm-objcopy.

Reviewed by: jakehehrlich, MaskRay

Differential Revision: https://reviews.llvm.org/D63820

llvm-svn: 365042
2019-07-03 14:21:48 +00:00
Simon Pilgrim
aecf76eaad [X86][AVX] combineX86ShuffleChainWithExtract - add number of non-zero extract_subvectors to the combine depth
This better accounts for the cost/benefit of removing extract_subvectors from the shuffle and will be more useful in future patches.

The vpermq predicate regression will be fixed shortly.

llvm-svn: 365041
2019-07-03 14:17:21 +00:00
Eugene Leviant
a4bd29ba06 [ThinLTO] Optimize writeonly globals out
Differential revision: https://reviews.llvm.org/D63444

llvm-svn: 365040
2019-07-03 14:14:52 +00:00
Owen Reynolds
b1b8c2c4a3 [llvm-ar][test] Add to MRI test coverage
This reapplies 363232 that was reverted due to a buildbot test failure, this build bot has now been fixed.

Differential Revision: https://reviews.llvm.org/D63197

llvm-svn: 365039
2019-07-03 13:47:29 +00:00
Simon Atanasyan
303ac16b7c [mips] Mark general scheduling model as complete
llvm-svn: 365034
2019-07-03 12:28:05 +00:00
Simon Atanasyan
3e3ce7afa8 [mips] Add missing atomic instructions to general scheduling definitions
llvm-svn: 365033
2019-07-03 12:27:58 +00:00
Simon Atanasyan
9c7be48c15 [mips] Add missing microMIPS instructions to general scheduling definitions
llvm-svn: 365032
2019-07-03 12:27:51 +00:00
Simon Pilgrim
0ea1436ffb [X86][SSE] lowerUINT_TO_FP_v2i32 - explicitly cast half word to double
Fixes MSVC analyzer extension->double warning.

llvm-svn: 365027
2019-07-03 11:23:27 +00:00
Simon Pilgrim
184b95034d [X86][SSE] LowerINSERT_VECTOR_ELT - ensure insertion index correctness. NFCI.
Assert that the insertion index is in range and use uint64_t for the index to fix MSVC/cppcheck truncation warning.

llvm-svn: 365025
2019-07-03 10:59:52 +00:00
Simon Pilgrim
545ef07c7b [X86][SSE] LowerScalarImmediateShift - ensure shift amount correctness. NFCI.
Assert that the shift amount is in range and create vXi8 shift masks in a way that doesn't cause MSVC/cppcheck shift result is truncated then extended warnings.

llvm-svn: 365024
2019-07-03 10:47:33 +00:00
Simon Atanasyan
ebf6cb2894 [mips] Add SIGRIE,GINVI,GINVT to general scheduling definitions
llvm-svn: 365023
2019-07-03 10:33:16 +00:00
Simon Atanasyan
6c88bb8ef4 [mips] Add missing mips16 instructions to general scheduling definitions
llvm-svn: 365022
2019-07-03 10:33:09 +00:00
Simon Atanasyan
1160ca80fa [mips] Add missing MSA and ASE instructions to general scheduling definitions
llvm-svn: 365021
2019-07-03 10:33:01 +00:00
Simon Atanasyan
a224d334a2 [mips] Replace some itineraries by instructions in the general scheduling definitions
llvm-svn: 365020
2019-07-03 10:32:54 +00:00
Simon Pilgrim
62aa643c0e Fix uninitialized variable warnings. NFCI.
Both MSVC and cppcheck don't like the fact that the variables are initialized via references.

llvm-svn: 365018
2019-07-03 10:22:08 +00:00
Simon Pilgrim
bf6d6d2f13 [X86] LowerFunnelShift - use modulo constant shift amount.
This avoids the use of getZExtValue and uses the modulo shift amount which is whats expected for funnel shifts anyhow. 

llvm-svn: 365016
2019-07-03 10:04:16 +00:00
Oliver Stannard
e6ef9c7af1 [ARM] Thumb2: favor R4-R7 over R12/LR in allocation order when opt for minsize
For Thumb2, we prefer low regs (costPerUse = 0) to allow narrow
encoding. However, current allocation order is like:
  R0-R3, R12, LR, R4-R11

As a result, a lot of instructs that use R12/LR will be wide instrs.

This patch changes the allocation order to:
  R0-R7, R12, LR, R8-R11
for thumb2 and -Osize.

In most cases, there is no extra push/pop instrs as they will be folded
into existing ones. There might be slight performance impact due to more
stack usage, so we only enable it when opt for min size.

https://reviews.llvm.org/D30324

llvm-svn: 365014
2019-07-03 09:58:52 +00:00
Sven van Haastregt
6f97dc2303 Remove some autoconf references from docs and comments
The autoconf build system support has been removed a while ago, remove
some outdated references.

Differential Revision: https://reviews.llvm.org/D63608

llvm-svn: 365013
2019-07-03 09:57:59 +00:00
Roman Lebedev
d508fa7e34 [InstCombine] Y - ~X --> X + Y + 1 fold (PR42457)
Summary:
I *think* we'd want this new variant, because we obviously
have better handling for `add` as compared to `sub`/`not`.

https://rise4fun.com/Alive/WMn

Fixes [[ https://bugs.llvm.org/show_bug.cgi?id=42457 | PR42457 ]]

Reviewers: spatel, nikic, huihuiz, efriedma

Reviewed By: spatel

Subscribers: RKSimon, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D63992

llvm-svn: 365011
2019-07-03 09:41:50 +00:00
Roman Lebedev
57458dafa4 [Codegen][X86][AArch64][ARM][PowerPC] Inc-of-add vs sub-of-not (PR42457)
Summary:
This is the backend part of [[ https://bugs.llvm.org/show_bug.cgi?id=42457 | PR42457 ]].
In middle-end, we'd want to prefer the form with two adds - D63992,
but as this diff shows, not every target will prefer that pattern.

Out of 4 targets for which i added tests all seem to be ok with inc-of-add for scalars,
but only X86 prefer that same pattern for vectors.

Here i'm adding a new TLI hook, always defaulting to the inc-of-add,
but adding AArch64,ARM,PowerPC overrides to prefer inc-of-add only for scalars.

Reviewers: spatel, RKSimon, efriedma, t.p.northover, hfinkel

Reviewed By: efriedma

Subscribers: nemanjai, javed.absar, kristof.beyls, kbarton, jsji, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64090

llvm-svn: 365010
2019-07-03 09:41:35 +00:00
Eugene Leviant
09de46cd5e [SCEV][LSR] Prevent using undefined value in binops
On some occasions ReuseOrCreateCast may convert previously
expanded value to undefined. That value may be passed by
SCEVExpander as an argument to InsertBinop making IV chain
undefined.

Differential revision: https://reviews.llvm.org/D63928 

llvm-svn: 365009
2019-07-03 09:36:32 +00:00
Alexander Potapenko
5dee8ef73f MSan: handle callbr instructions
Summary:
Handling callbr is very similar to handling an inline assembly call:
MSan must checks the instruction's inputs.
callbr doesn't (yet) have outputs, so there's nothing to unpoison,
and conservative assembly handling doesn't apply either.

Fixes PR42479.

Reviewers: eugenis

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64072

llvm-svn: 365008
2019-07-03 09:28:50 +00:00
Serguei Katkov
9b87d63503 [LoopPeel] Re-factor llvm::peelLoop method. NFC.
Extract code dealing with branch weights in separate functions.

Reviewers: reames, mkuper, iajbar, fhahn
Reviewed By: reames, fhahn
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D63917

llvm-svn: 365002
2019-07-03 05:59:23 +00:00
Jordan Rupprecht
3ef3977b58 Revert [InlineCost] cleanup calculations of Cost and Threshold
This reverts r364422 (git commit 1a3dc761860d620ac8ed7e32a4285952142f780b)

The inlining cost calculation is incorrect, leading to stack overflow due to large stack frames from heavy inlining.

llvm-svn: 365000
2019-07-03 04:01:51 +00:00
Teresa Johnson
e843f33c23 [ThinLTO] Reenable test with workaround for known failure
Reenable the testing disabled in r364978 with the same workaround used
for this failure in the cfi-devirt.ll test. The known issue is PR39436,
and the workaround is to add -verify-machineinstrs=0.

llvm-svn: 364997
2019-07-03 02:14:47 +00:00
Michael Liao
685d2b5b50 [AMDGPU] Enable serializing of argument info.
Summary:
- Support serialization of all arguments in machine function info. This
  enables fabricating MIR tests depending on argument info.

Reviewers: arsenm, rampitec

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64096

llvm-svn: 364995
2019-07-03 02:00:21 +00:00