1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-21 12:02:58 +02:00
Commit Graph

18 Commits

Author SHA1 Message Date
Reed Kotler
dc9a2e4d7b Mips16 does not use register scavenger from TargetRegisterInfo. It allocates
a RegScavenger object on it's own.
 

llvm-svn: 182430
2013-05-21 22:06:02 +00:00
Richard Sandiford
be8189863a [mips] Fix the head Mips16RegisterInfo.cpp comment
...aka a test commit.

llvm-svn: 180936
2013-05-02 18:28:03 +00:00
Akira Hatanaka
251bd9f852 [mips] Define a function which returns the GPR register class.
llvm-svn: 178359
2013-03-29 19:17:42 +00:00
Eli Bendersky
37f247b8d8 Move the eliminateCallFramePseudoInstr method from TargetRegisterInfo
to TargetFrameLowering, where it belongs. Incidentally, this allows us
to delete some duplicated (and slightly different!) code in TRI.

There are potentially other layering problems that can be cleaned up
as a result, or in a similar manner.

The refactoring was OK'd by Anton Korobeynikov on llvmdev.

Note: this touches the target interfaces, so out-of-tree targets may
be affected.

llvm-svn: 175788
2013-02-21 20:05:00 +00:00
Reed Kotler
434681ac07 When Mips16 frames grow large, the immediate field may exceed the maximum
allowed size for the instruction. This code uses RegScavenger to fix this.
We sometimes need 2 registers for Mips16 so we must handle things
differently than how register scavenger is normally used.

llvm-svn: 174696
2013-02-08 03:57:41 +00:00
Chandler Carruth
4c1f3c24db Move all of the header files which are involved in modelling the LLVM IR
into their new header subdirectory: include/llvm/IR. This matches the
directory structure of lib, and begins to correct a long standing point
of file layout clutter in LLVM.

There are still more header files to move here, but I wanted to handle
them in separate commits to make tracking what files make sense at each
layer easier.

The only really questionable files here are the target intrinsic
tablegen files. But that's a battle I'd rather not fight today.

I've updated both CMake and Makefile build systems (I think, and my
tests think, but I may have missed something).

I've also re-sorted the includes throughout the project. I'll be
committing updates to Clang, DragonEgg, and Polly momentarily.

llvm-svn: 171366
2013-01-02 11:36:10 +00:00
Reed Kotler
d8213f114a Call llvm_unreachable instead of assert.
llvm-svn: 170822
2012-12-21 00:44:59 +00:00
Reed Kotler
4796d835c7 There is one more patch to finish large frames. Make sure we assert
on code that has large frames which will not yet compile correctly.

llvm-svn: 170673
2012-12-20 06:57:00 +00:00
Reed Kotler
53002f4e46 Turn on register scavenger for Mips 16
We use an unused Mips 32 register for the emergency slot
instead of using the stack.

llvm-svn: 170665
2012-12-20 04:44:58 +00:00
Chandler Carruth
a490793037 Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.

Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]

llvm-svn: 169131
2012-12-03 16:50:05 +00:00
Reed Kotler
82a7f09a30 Implement ADJCALLSTACKUP and ADJCALLSTACKDOWN
llvm-svn: 167107
2012-10-31 05:21:10 +00:00
Reed Kotler
16eaf8644a This patch is for the implementation of mips16 complex pattern addr16.
Previously mips16 was sharing the pattern addr which is used for mips32
and mips64. This had a number of problems:
1) Storing and loading byte and halfword quantities for mips16 has particular
problems due to the primarily non mips16 nature of SP. When we must
load/store byte/halfword stack objects in a function, we must create a mips16
alias register for SP. This functionality is tested in stchar.ll.
2) We need to have an FP register under certain conditions (such as 
dynamically sized alloca). We use mips16 register S0 for this purpose.
In this case, we also use this register when accessing frame objects so this
issue also affects the complex pattern addr16. This functionality is
tested in alloca16.ll.

The Mips16InstrInfo.td has been updated to use addr16 instead of addr.

The complex pattern C++ function for addr has been copied to addr16 and
updated to reflect the above issues.

llvm-svn: 166897
2012-10-28 06:02:37 +00:00
Akira Hatanaka
91bf56ac6c Delete member MipsFunctionInfo::OutArgFIRange and code that accesses it.
llvm-svn: 164718
2012-09-26 19:18:19 +00:00
Craig Topper
68f6b47a37 Remove unused private field to silence build warning.
llvm-svn: 162426
2012-08-23 04:45:31 +00:00
Akira Hatanaka
679d5c8fd7 Add a member of type Mips16InstrInfo/MipsSEInstrInfo to class
Mips16RegisterInfo/MipsSERegisterInfo. 

No changes in functionality.

llvm-svn: 162413
2012-08-22 23:58:53 +00:00
Akira Hatanaka
ebbe0eff91 1. Redo mips16 instructions to avoid multiple opcodes for same instruction.
Change these to patterns.
2. Add another 16 instructions.

Patch by Reed Kotler.

llvm-svn: 161272
2012-08-03 22:57:02 +00:00
Akira Hatanaka
c43e6b2166 Implement MipsSERegisterInfo::eliminateCallFramePseudoInstr. The function emits
instructions that decrement and increment the stack pointer before and after a
call when the function does not have a reserved call frame.

llvm-svn: 161093
2012-07-31 23:52:55 +00:00
Akira Hatanaka
24dddbed36 Add definitions of two subclasses of MipsRegisterInfo, Mips16RegisterInfo and
MipsSERegisterInfo.

llvm-svn: 161092
2012-07-31 23:41:32 +00:00