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Author SHA1 Message Date
Chad Rosier
0d70d716e9 [AArch64] Add support for lowering bitreverse to the rbit instruction. 
Differential Revision: https://reviews.llvm.org/D28379

llvm-svn: 291575
 2017-01-10 17:20:33 +00:00
Yi Kong
57329b1cc2 ARM: Fix codegen for rbit intrinsic 
LLVM generates illegal `rbit r0, #352` instruction for rbit intrinsic.
According to ARM ARM, rbit only takes register as argument, not immediate.
The correct instruction should be rbit <Rd>, <Rm>.

The bug was originally introduced in r211057.

Differential Revision: http://reviews.llvm.org/D4980

llvm-svn: 216064
 2014-08-20 10:40:20 +00:00