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Author SHA1 Message Date
NAKAMURA Takumi
1b89cab2ca Whitespace. 
llvm-svn: 163289
 2012-09-06 03:02:56 +00:00
NAKAMURA Takumi
2c109dd4b6 Unix/Signals.inc: Fix a typo. Thanks to Dani Berg! 
llvm-svn: 163288
 2012-09-06 03:01:43 +00:00
Jack Carter
43a54f6830 There are some Mips instructions that are lowered by the 
assembler such as shifts greater than 32. In the case 
of direct object, the code gen needs to do this lowering 
since the assembler is not involved.

With the advent of the llvm-mc assembler, it also needs 
to do the same lowering.

This patch makes that specific lowering code accessible 
to both the direct object output and the assembler.

This patch does not affect generated output.

llvm-svn: 163287
 2012-09-06 02:31:34 +00:00
Jim Grosbach
0a077abacb Update function names to conform to guidelines. 
No functional change.

llvm-svn: 163279
 2012-09-06 00:59:08 +00:00
Jack Carter
2a8cbd60d3 Mips specific llvm assembler support for branch and jump instructions. 
Test case included.

Contributer: Vladimir Medic
llvm-svn: 163277
 2012-09-06 00:43:26 +00:00
Jakob Stoklund Olesen
826d399ee6 Remove predicated pseudo-instructions. 
These pseudos are no longer needed now that it is possible to represent
predicated instructions in SSA form.

llvm-svn: 163275
 2012-09-05 23:58:04 +00:00
Jakob Stoklund Olesen
0324528c8c Use predication instead of pseudo-opcodes when folding into MOVCC. 
Now that it is possible to dynamically tie MachineInstr operands,
predicated instructions are possible in SSA form:

  %vreg3<def> = SUBri %vreg1, -2147483647, pred:14, pred:%noreg, %opt:%noreg
  %vreg4<def,tied1> = MOVCCr %vreg3<tied0>, %vreg1, %pred:12, pred:%CPSR

Becomes a predicated SUBri with a tied imp-use:

  SUBri %vreg1, -2147483647, pred:13, pred:%CPSR, opt:%noreg, %vreg1<imp-use,tied0>

This means that any instruction that is safe to move can be folded into
a MOVCC, and the *CC pseudo-instructions are no longer needed.

The test case changes reflect that Thumb2SizeReduce recognizes the
predicated instructions. It didn't understand the pseudos.

llvm-svn: 163274
 2012-09-05 23:58:02 +00:00
Chad Rosier
e37b2608d9 [ms-inline asm] Use the asm dialect from the MI to set the parser dialect. 
llvm-svn: 163273
 2012-09-05 23:57:37 +00:00
Manman Ren
7459dd03a2 JumpThreading: when default destination is the destination of some cases in a 
switch, make sure we include the value for the cases when calculating edge
value from switch to the default destination.

rdar://12241132

llvm-svn: 163270
 2012-09-05 23:45:58 +00:00
Jack Carter
f7221de872 Mips specific llvm assembler support for ALU instructions. This includes 
register support. Test case included.

Contributer: Vladimir Medic
llvm-svn: 163268
 2012-09-05 23:34:03 +00:00
Chad Rosier
53ddf04a70 Cleanup a few magic numbers. 
llvm-svn: 163263
 2012-09-05 22:40:13 +00:00
Roman Divacky
85348270cd Stop casting away const qualifier needlessly. 
llvm-svn: 163258
 2012-09-05 22:26:57 +00:00
Chad Rosier
5d0b8f95cc [ms-inline asm] We only need one bit to represent the AsmDialect in the 
MachineInstr.

llvm-svn: 163257
 2012-09-05 22:17:43 +00:00
Roman Divacky
a6678a5602 Constify this properly. Found by gcc48 -Wcast-qual. 
llvm-svn: 163256
 2012-09-05 22:15:49 +00:00
Roman Divacky
84d5745fdc Mark checkSignature const, and in turn stop casting away const from 
ArchiveMemberHeader. Found by gcc48 -Wcast-qual.

llvm-svn: 163255
 2012-09-05 22:09:23 +00:00
Roman Divacky
4906050a4d Constify SDNodeIterator an stop its only non-const user being cast stripped 
of its constness. Found by gcc48 -Wcast-qual.

llvm-svn: 163254
 2012-09-05 22:03:34 +00:00
Roman Divacky
865ac925b9 Constify subtarget info properly so that we dont cast away the const in 
the SubtargetInfoKV tables. Found by gcc48 -Wcast-qual.

llvm-svn: 163251
 2012-09-05 21:43:57 +00:00
Roman Divacky
4be967f49b Use const properly so that we dont remove const qualifier from region and MII 
by casting. Found with gcc48.

llvm-svn: 163247
 2012-09-05 21:17:34 +00:00
Chad Rosier
f7a06e33a3 [ms-inline asm] Propagate the asm dialect into the MachineInstr representation. 
llvm-svn: 163243
 2012-09-05 21:00:58 +00:00
Hal Finkel
a414a44e22 Move the PPC TOC defs into the PPC64 InstrInfo file. 
Since TOC is just defined for PPC64, move its definition to PPC64 td file.

Patch by Adhemerval Zanella.

llvm-svn: 163234
 2012-09-05 19:22:27 +00:00
Chad Rosier
542e938cf4 [ms-inline asm] Enumerate the InlineAsm dialects and rename the nsdialect to 
inteldialect.

llvm-svn: 163231
 2012-09-05 19:00:49 +00:00
Tim Northover
4e03b89c79 Strip old MachineInstrs *after* we know we can put them back. 
Previous patch accidentally decided it couldn't convert a VFP to a
NEON instruction after it had already destroyed the old one. Not a
good move.

llvm-svn: 163230
 2012-09-05 18:37:53 +00:00
Roman Divacky
4c161d6fab Remove unused typedefs gcc4.8 warns about. 
llvm-svn: 163225
 2012-09-05 17:55:46 +00:00
Jim Grosbach
cab7015180 MCJIT: getPointerToFunction() references target address space. 
Make sure to return a pointer into the target memory, not the local memory.
Often they are the same, but we can't assume that.

llvm-svn: 163217
 2012-09-05 16:50:40 +00:00
Benjamin Kramer
8f45a80d73 Switch BasicAliasAnalysis' cache to SmallDenseMap. 
It relies on clear() being fast and the cache rarely has more than 1 or 2
elements, so give it an inline capacity and always shrink it back down in case
it grows. DenseMap will grow to 64 buckets which makes clear() a lot slower.

llvm-svn: 163215
 2012-09-05 16:49:37 +00:00
Pranav Bhandarkar
876ff208b6 LLVM Bug Fix 13709: Remove needless lsr(Rp, #32) instruction access the 
subreg_hireg of register pair Rp.

	* lib/Target/Hexagon/HexagonPeephole.cpp(PeepholeDoubleRegsMap): New
	 DenseMap similar to PeepholeMap that additionally records subreg info
	 too.
        (runOnMachineFunction): Record information in PeepholeDoubleRegsMap
        and copy propagate the high sub-reg of Rp0 in Rp1 = lsr(Rp0, #32) to
	the instruction Rx = COPY Rp1:logreg_subreg.
	* test/CodeGen/Hexagon/remove_lsr.ll: New test.
	

llvm-svn: 163214
 2012-09-05 16:01:40 +00:00
Kostya Serebryany
9330f23483 [asan] fix lint 
llvm-svn: 163205
 2012-09-05 09:00:18 +00:00
Silviu Baranga
6f46bb1705 Fixed the DAG combiner to better handle the folding of AND nodes for vector types. The previous code was making the assumption that the length of the bitmask returned by isConstantSplat was equal to the size of the vector type. Now we first make sure that the splat value has at least the length of the vector lane type, then we only use as many fields as we have available in the splat value. 
llvm-svn: 163203
 2012-09-05 08:57:21 +00:00
Kostya Serebryany
a56cf96db5 [asan] extend the blacklist functionality to handle global-init. Patch by Reid Watson 
llvm-svn: 163199
 2012-09-05 07:29:56 +00:00
Craig Topper
864ef1eec5 Remove some of the patterns added in r163196. Increasing the complexity on insert_subvector into undef accomplishes the same thing. 
llvm-svn: 163198
 2012-09-05 07:26:35 +00:00
Craig Topper
f029cfe913 Add patterns for integer forms of VINSERTF128/VINSERTI128 folded with loads. Also add patterns to turn subvector inserts with loads to index 0 of an undef into VMOVAPS. 
llvm-svn: 163196
 2012-09-05 06:58:39 +00:00
Chad Rosier
d18aee2236 Add a FIXME that assumes we maintain backward compatibility until the next major release. 
llvm-svn: 163195
 2012-09-05 06:28:52 +00:00
Logan Chien
d6babb951e Reorder the comments of EmitExceptionTable. 
llvm-svn: 163194
 2012-09-05 06:28:26 +00:00
Logan Chien
a15abb3d65 Fix UseInitArray option for MIPS target. 
llvm-svn: 163193
 2012-09-05 06:17:17 +00:00
Craig Topper
6274d26545 Convert vextracti128/vextractf128 intrinsics to extract_subvector at DAG build time. Similar was previously done for vinserti128/vinsertf128. Add patterns for folding these extract_subvectors with stores. 
llvm-svn: 163192
 2012-09-05 05:48:09 +00:00
Richard Smith
8213d2a51b Remove redundant semicolons to fix -pedantic-errors build. 
llvm-svn: 163190
 2012-09-05 01:41:37 +00:00
Chad Rosier
b75afa43e4 Fix function name per coding standard. 
llvm-svn: 163187
 2012-09-05 01:15:43 +00:00
Chad Rosier
00a82f13af [ms-inline asm] Add support for the nsdialect keyword in the Bitcode 
Reader/Writer.

llvm-svn: 163185
 2012-09-05 00:56:20 +00:00
Chad Rosier
aaab764144 [ms-inline asm] Add the nsdialect keyword to the lexer. 
llvm-svn: 163184
 2012-09-05 00:51:02 +00:00
Chad Rosier
aaee8ac173 [ms-inline asm] Emit the (new) inline asm Non-Standard Dialect attribute. 
llvm-svn: 163181
 2012-09-05 00:08:17 +00:00
Dan Gohman
e90f78d5cd Make provenance checking conservative in cases when 
pointers-to-strong-pointers may be in play. These can lead to retains and
releases happening in unstructured ways, foiling the optimizer. This fixes
rdar://12150909.

llvm-svn: 163180
 2012-09-04 23:16:20 +00:00
Jakub Staszak
fea8f898f4 BypassSlowDivision: Assign to reference, don't copy the object. 
llvm-svn: 163179
 2012-09-04 23:11:11 +00:00
Jakob Stoklund Olesen
2cda807309 Search the whole instruction for tied operands. 
Implicit uses can be dynamically tied to defs. This will soon be used
for predicated instructions on ARM.

llvm-svn: 163177
 2012-09-04 22:59:30 +00:00
Chad Rosier
46ed647f1e [ms-inline asm] Add the inline assembly dialect, AsmDialect, to the InlineAsm 
class.

llvm-svn: 163175
 2012-09-04 22:46:24 +00:00
Chad Rosier
b049a3421f [ms-inline asm] Remove the Inline Asm Non-Standard Dialect attribute. This 
implementation does not co-exist well with how the sideeffect and alignstack
attributes are handled.  The reverts r161641.

llvm-svn: 163174
 2012-09-04 22:29:45 +00:00
Jakub Staszak
a5fd74206a Fix my previous patch (r163164). It does now what it is supposed to do: 
Doesn't set MadeChange to TRUE if BypassSlowDivision doesn't change anything.

llvm-svn: 163165
 2012-09-04 21:16:59 +00:00
Jakub Staszak
b2faa176c4 Return false if BypassSlowDivision doesn't change anything. 
Also a few minor changes:
- use pre-inc instead of post-inc
- use isa instead of dyn_cast
- 80 col
- trailing spaces

llvm-svn: 163164
 2012-09-04 20:48:24 +00:00
Jakob Stoklund Olesen
50ac7b577c Typo. 
llvm-svn: 163154
 2012-09-04 18:44:43 +00:00
Jakob Stoklund Olesen
a017c9c48b Actually use the MachineOperand field for isRegTiedToDefOperand(). 
The MachineOperand::TiedTo field was maintained, but not used.

This patch enables it in isRegTiedToDefOperand() and
isRegTiedToUseOperand() which are the actual functions use by the
register allocator.

llvm-svn: 163153
 2012-09-04 18:43:25 +00:00
Jakob Stoklund Olesen
ef5dcf47b8 Move tie checks into MachineVerifier::visitMachineOperand. 
llvm-svn: 163152
 2012-09-04 18:38:28 +00:00