RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-26 04:32:44 +01:00
Code Issues Projects Releases Wiki Activity
23,288 Commits 4 Branches 5 Tags 704 MiB
1bd0aaf2b8
Commit Graph

1183 Commits

Author SHA1 Message Date
Chris Lattner
1bd0aaf2b8 rename these nodes 
llvm-svn: 26848
 2006-03-19 01:13:28 +00:00
Nate Begeman
793c8136ae Fix subfic to match subc by default instead of sub so that it is correctly 
cost-modeled as producing a flag.  This fixes the test I just added for neg

llvm-svn: 26835
 2006-03-17 22:41:37 +00:00
Nate Begeman
42736d46b2 Remove BRTWOWAY* 
Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.

llvm-svn: 26814
 2006-03-17 01:40:33 +00:00
Chris Lattner
87dbd49cbe remove dead variable 
llvm-svn: 26813
 2006-03-16 23:52:08 +00:00
Nate Begeman
63c4456867 Notes on how to kill the eeevil brtwoway, and make ppc branch selector 
more target independant, generate better code, and be less conservative.

llvm-svn: 26809
 2006-03-16 22:37:48 +00:00
Chris Lattner
f2008cb73b Strangely, calls clobber call-clobbered vector regs. Whodathoughtit? 
llvm-svn: 26808
 2006-03-16 22:35:59 +00:00
Chris Lattner
8a756c5171 add a note 
llvm-svn: 26807
 2006-03-16 22:25:55 +00:00
Chris Lattner
57773fdac1 teach the ppc backend how to spill/reload vector regs 
llvm-svn: 26806
 2006-03-16 22:24:02 +00:00
Chris Lattner
661ee5d3c1 add callee saved vector regs 
llvm-svn: 26805
 2006-03-16 22:07:06 +00:00
Evan Cheng
cad75d9f0c Added a way for TargetLowering to specify what values can be used as the 
scale component of the target addressing mode.

llvm-svn: 26802
 2006-03-16 21:47:42 +00:00
Chris Lattner
7f5361757b in functions that use a lot of callee saved regs, this can be more than 
5 instructions away.

llvm-svn: 26801
 2006-03-16 21:31:45 +00:00
Chris Lattner
bf153651b1 Add support for copying registers. still needed: spilling and reloading them 
llvm-svn: 26800
 2006-03-16 20:03:58 +00:00
Nate Begeman
cbca1b3d14 Another case we could do better on. 
llvm-svn: 26795
 2006-03-16 18:50:44 +00:00
Chris Lattner
b5d0896994 Save/restore VRSAVE once per function, not once per block. 
llvm-svn: 26793
 2006-03-16 18:25:23 +00:00
Nate Begeman
e371cb595a Update scheduling info for vrsave instruction 
llvm-svn: 26776
 2006-03-15 05:25:05 +00:00
Chris Lattner
392087f5bd Fix an off by one error that caused PPC LLC failures last night. 
llvm-svn: 26758
 2006-03-14 17:56:49 +00:00
Evan Cheng
ae7469b2c5 PPC LSR pass should use target lowering hooks. 
llvm-svn: 26743
 2006-03-13 23:56:51 +00:00
Evan Cheng
7ec94f2ff7 Added getTargetLowering() to TargetMachine. Refactored targets to support this. 
llvm-svn: 26742
 2006-03-13 23:20:37 +00:00
Chris Lattner
d0505331d2 For functions that use vector registers, save VRSAVE, mark used 
registers, and update it on entry to each function, then restore it on exit.

This compiles:

void func(vfloat *a, vfloat *b, vfloat *c) {
        *a = *b * *c + *c;
}

to this:

_func:
        mfspr r2, 256
        oris r6, r2, 49152
        mtspr 256, r6
        lvx v0, 0, r5
        lvx v1, 0, r4
        vmaddfp v0, v1, v0, v0
        stvx v0, 0, r3
        mtspr 256, r2
        blr

GCC produces this (which has additional stack accesses):

_func:
        mfspr r0,256
        stw r0,-4(r1)
        oris r0,r0,0xc000
        mtspr 256,r0
        lvx v0,0,r5
        lvx v1,0,r4
        lwz r12,-4(r1)
        vmaddfp v0,v0,v1,v0
        stvx v0,0,r3
        mtspr 256,r12
        blr

llvm-svn: 26733
 2006-03-13 21:52:10 +00:00
Chris Lattner
3aff8e6acf Fix a couple of bugs that broke the alpha tester build 
llvm-svn: 26722
 2006-03-13 05:23:59 +00:00
Chris Lattner
9898674f99 Handle cracked instructions in dispatch group formation. 
llvm-svn: 26721
 2006-03-13 05:20:04 +00:00
Chris Lattner
ba10d4e4ab Mark instructions that are cracked by the PPC970 decoder as such. 
llvm-svn: 26720
 2006-03-13 05:15:10 +00:00
Chris Lattner
a278639f29 Several big changes: 
1. Use flags on the instructions in the .td file to indicate the PPC970 unit
   type instead of a table in the .cpp file.  Much cleaner.
2. Change the hazard recognizer to build d-groups according to the actual
   algorithm used, not my flawed understanding of it.
3. Model "must be in the first slot" and "must be the only instr in a group"
   accurately.

llvm-svn: 26719
 2006-03-12 09:13:49 +00:00
Chris Lattner
19b93158c1 blr is a branch too 
llvm-svn: 26710
 2006-03-11 21:49:49 +00:00
Chris Lattner
2370965e55 teach the JIT to encode vector registers 
llvm-svn: 26697
 2006-03-10 20:19:50 +00:00
Chris Lattner
3f23d22d3f Change the interface for getting a target HazardRecognizer to be more clean. 
llvm-svn: 26608
 2006-03-08 04:25:59 +00:00
Chris Lattner
24aa564456 add a note 
llvm-svn: 26605
 2006-03-08 00:25:47 +00:00
Jim Laskey
91d5ce2531 Use "llvm.metadata" section for debug globals. Filter out these globals in the 
asm printer.

llvm-svn: 26599
 2006-03-07 22:00:35 +00:00
Chris Lattner
27f87a6955 add another missing store. 
llvm-svn: 26595
 2006-03-07 16:26:48 +00:00
Chris Lattner
dfdeec73bc add a couple more load/store instrs, add a newline to the end of file. 
llvm-svn: 26594
 2006-03-07 16:19:46 +00:00
Nate Begeman
a8bc3c0c3c This kinda sorta implements "things that have to lead a dispatch group". 
llvm-svn: 26591
 2006-03-07 08:30:27 +00:00
Chris Lattner
842436586c add some new instructions to the classifier. With this, we correctly insert 
a nop into Freebench/neural, which speeds it up from 136->129s (~5.4%).

llvm-svn: 26590
 2006-03-07 07:14:55 +00:00
Chris Lattner
0cd4bd574c add some comments that describe what we model 
llvm-svn: 26588
 2006-03-07 06:44:19 +00:00
Chris Lattner
4cd6cd499d Implement a very very simple hazard recognizer for LSU rejects and ctr set/read 
flushes

llvm-svn: 26587
 2006-03-07 06:32:48 +00:00
Chris Lattner
ae34bbf56b add a note 
llvm-svn: 26585
 2006-03-07 04:42:59 +00:00
Chris Lattner
af44ead7f3 implement TII::insertNoop 
llvm-svn: 26562
 2006-03-05 23:49:55 +00:00
Chris Lattner
6b0947c277 Copysign needs to be expanded everywhere. Note that Alpha and IA64 should 
implement copysign as a native op if they have it.

llvm-svn: 26541
 2006-03-05 05:08:37 +00:00
Chris Lattner
317021b6c4 Implement CodeGen/PowerPC/or-addressing-mode.ll, which is also PR668. 
llvm-svn: 26450
 2006-03-01 07:14:48 +00:00
Chris Lattner
caec0d887c add a note 
llvm-svn: 26448
 2006-03-01 06:36:20 +00:00
Chris Lattner
137c02aa60 Compile this: 
void foo(float a, int *b) { *b = a; }

to this:

_foo:
        fctiwz f0, f1
        stfiwx f0, 0, r4
        blr

instead of this:

_foo:
        fctiwz f0, f1
        stfd f0, -8(r1)
        lwz r2, -4(r1)
        stw r2, 0(r4)
        blr

This implements CodeGen/PowerPC/stfiwx.ll, and also incidentally does the
right thing for GCC bugzilla 26505.

llvm-svn: 26447
 2006-03-01 05:50:56 +00:00
Chris Lattner
6ba976b557 Use a target-specific dag-combine to implement CodeGen/PowerPC/fp-int-fp.ll. 
llvm-svn: 26445
 2006-03-01 04:57:39 +00:00
Evan Cheng
ebe1f272b7 Vector op lowering. 
llvm-svn: 26438
 2006-03-01 01:11:20 +00:00
Chris Lattner
9f70a7924d Add a subtarget feature for the stfiwx instruction. I know the G5 has it, 
but I don't know what other PPC impls do.  If someone could update the proc
table, I would appreciate it :)

llvm-svn: 26421
 2006-02-28 07:08:22 +00:00
Chris Lattner
866634d77f remove implemented item 
llvm-svn: 26418
 2006-02-28 06:36:04 +00:00
Nate Begeman
56a4dafd8d readme updates 
llvm-svn: 26405
 2006-02-27 22:08:36 +00:00
Chris Lattner
bc35137363 Add memory printing support for PPC. Input memory operands now work with 
inline asms! :)

llvm-svn: 26365
 2006-02-24 20:27:40 +00:00
Chris Lattner
3d451516ec Implement selection of inline asm memory operands 
llvm-svn: 26348
 2006-02-24 02:13:12 +00:00
Evan Cheng
2720cd1d7e PPC JIT relocation model should be DynamicNoPIC. 
llvm-svn: 26338
 2006-02-23 22:18:07 +00:00
Chris Lattner
cdbd9d6d4c Implement the PPC inline asm "L" modifier. This allows us to compile: 
long long test(long long X) {
  __asm__("foo %0 %L0 %1 %L1" : "=r"(X): "r"(X));
  return X;
}

to:
        foo r2 r3 r2 r3

llvm-svn: 26333
 2006-02-23 19:31:10 +00:00
Evan Cheng
305141c1ba - Added option -relocation-model to set relocation model. Valid values include static, pic, 
dynamic-no-pic, and default.
PPC and x86 default is dynamic-no-pic for Darwin, pic for others.
- Removed options -enable-pic and -ppc-static.

llvm-svn: 26315
 2006-02-22 20:19:42 +00:00