Jakob Stoklund Olesen
216f6cc9ae
Remove Predicate_* calls from MBlaze and XCore
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llvm-svn: 112920
2010-09-03 00:35:16 +00:00
Eric Christopher
2dae43dbe4
Remove isTwoAddress from XCore.
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llvm-svn: 106446
2010-06-21 18:51:38 +00:00
Chris Lattner
4de7f7e862
fix a type contradition: XCoreISD::RETSP has one argument, not zero.
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llvm-svn: 99760
2010-03-28 08:47:39 +00:00
Chris Lattner
896b393fab
set SDNPVariadic on nodes throughout the rest of the targets that
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need them.
llvm-svn: 98937
2010-03-19 05:33:51 +00:00
Richard Osborne
92fb0be76b
Don't mark call instruction as a barrier.
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llvm-svn: 96983
2010-02-23 21:08:11 +00:00
Richard Osborne
eb0446c12a
ECALLF, ECALLT shouldn't be marked as barriers.
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llvm-svn: 96964
2010-02-23 18:29:49 +00:00
Richard Osborne
9abd3b3ca7
Mark unconditional branches as barriers. Found using -verify-machineinstrs
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llvm-svn: 96960
2010-02-23 18:13:38 +00:00
Richard Osborne
7387249531
Lower BR_JT on the XCore to a jump into a series of jump instructions.
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llvm-svn: 96942
2010-02-23 13:25:07 +00:00
Dan Gohman
92b6122204
Fix "the the" and similar typos.
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llvm-svn: 95781
2010-02-10 16:03:48 +00:00
Richard Osborne
fc2d5141a4
Add XCore support for indirectbr / blockaddress.
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llvm-svn: 89273
2009-11-18 23:20:42 +00:00
Dan Gohman
4631d78a3b
Set isBarrier = 1 on return instructions, as they are control barriers.
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llvm-svn: 86851
2009-11-11 18:11:07 +00:00
Dan Gohman
3393a4c997
Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a
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bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.
llvm-svn: 85517
2009-10-29 18:10:34 +00:00
Richard Osborne
1719935e3f
Add some peepholes for signed comparisons using ashr X, X, 32.
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llvm-svn: 83549
2009-10-08 15:38:17 +00:00
Richard Osborne
90a7ea5c13
Remove xs1b predicate since it is no longer needed to differentiate betweem
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xs1a and xs1b.
llvm-svn: 83383
2009-10-06 16:17:57 +00:00
Richard Osborne
b692ade672
Remove xs1a subtarget. xs1a is a preproduction device used in
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early development boards which is no longer supported in the
XMOS toolchain.
llvm-svn: 83381
2009-10-06 16:01:09 +00:00
Richard Osborne
179bf3bdc2
Add extra SEXT pattern.
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llvm-svn: 77920
2009-08-02 22:45:24 +00:00
Richard Osborne
bdd120fbdb
Fix pattern for LD16S_3r, add basic tests to check load / store instructions
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are being properly selected.
llvm-svn: 75797
2009-07-15 17:06:59 +00:00
Bill Wendling
8235a05c1a
Untabification.
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llvm-svn: 72604
2009-05-30 01:09:53 +00:00
Richard Osborne
12b88f2fae
Add pseudo instructions to the XCore for (load|store|load address) of a
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frame index. eliminateFrameIndex will replace these instructions with
(LDWSP|STWSP|LDAWSP) or (LDW|STW|LDAWF) if a frame pointer is in use.
This fixes PR 3324. Previously we used LDWSP, STWSP, LDAWSP before frame
pointer elimination. However since they were marked as implicitly using
SP they could not be rematerialised.
llvm-svn: 62238
2009-01-14 18:26:46 +00:00
Richard Osborne
e74ae9dbb7
Add support for ISD::TRAP to the XCore backend
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llvm-svn: 60479
2008-12-03 10:59:16 +00:00
Richard Osborne
8f86bb4d20
Add XCore intrinsics for getid (returns thread id) and bitrev (reverses
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bits in a word).
llvm-svn: 59296
2008-11-14 10:12:16 +00:00
Richard Osborne
acc7a27e24
Add XCore backend.
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llvm-svn: 58838
2008-11-07 10:59:00 +00:00
