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17077 Commits

Author SHA1 Message Date
Chris Lattner
1d534245fc add a note, progress unblocked by PR8575 being fixed. 
llvm-svn: 124599
 2011-01-31 20:23:28 +00:00
Anton Korobeynikov
b31576ae4d Save a mapping between original and cloned constpool entries. 
llvm-svn: 124570
 2011-01-30 22:07:39 +00:00
Benjamin Kramer
6b3c3de09a Teach DAGCombine to fold fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2) when c1 equals the amount of bits that are truncated off. 
This happens all the time when a smul is promoted to a larger type.

On x86-64 we now compile "int test(int x) { return x/10; }" into
  movslq  %edi, %rax
  imulq $1717986919, %rax, %rax
  movq  %rax, %rcx
  shrq  $63, %rcx
  sarq  $34, %rax <- used to be "shrq $32, %rax; sarl $2, %eax"
  addl  %ecx, %eax

This fires 96 times in gcc.c on x86-64.

llvm-svn: 124559
 2011-01-30 16:38:43 +00:00
Bob Wilson
e7ac2389b2 PR9030: Fix disassembly of ARM "mov pc, lr" instruction. 
Patch by Jyun-Yan You.

llvm-svn: 124492
 2011-01-28 17:50:30 +00:00
Evan Cheng
2042be8132 Fix PLD encoding. 
llvm-svn: 124458
 2011-01-27 23:48:34 +00:00
Kevin Enderby
ce1439297b Changed llvm-mc arm target to give an error if .syntax divided is used. Since 
only .syntax unified is supported.

llvm-svn: 124454
 2011-01-27 23:22:36 +00:00
David Greene
1f8b96494e [AVX] Clean up the code to configure target lowering for AVX. Specify 
how to lower more/new operations.  This is a prerequisite for adding
additional AVX lowering.

llvm-svn: 124447
 2011-01-27 22:38:56 +00:00
Roman Divacky
991a87e2e3 Introduce virtual ParseRegister method in TargetAsmParser. 
Create override of this method in X86/ARM/MBlaze.

llvm-svn: 124378
 2011-01-27 17:14:22 +00:00
Eric Christopher
9c446b2711 Use the incoming VT not the VT of where we're trying to store to determine 
if we can store a value. Also, the exclusion is or, not and.

Fixes rdar://8920247.

llvm-svn: 124357
 2011-01-27 05:44:56 +00:00
NAKAMURA Takumi
d418ff3b1a lib/Target/X86/X86ISelDAGToDAG.cpp: __main should be WINCALL64 on Win64. 
CALL64 marks %xmm* as dead.

llvm-svn: 124354
 2011-01-27 03:20:19 +00:00
Bill Wendling
5913724ac2 Add support for printing out floating point values from the ARM assembly 
parser. The parser will always give us a binary representation of the floating
point number.

llvm-svn: 124318
 2011-01-26 20:57:43 +00:00
David Greene
5c173a307b [AVX] Add INSERT_SUBVECTOR and support it on x86. This provides a 
default implementation for x86, going through the stack in a similr
fashion to how the codegen implements BUILD_VECTOR.  Eventually this
will get matched to VINSERTF128 if AVX is available.

llvm-svn: 124307
 2011-01-26 19:13:22 +00:00
David Greene
93b74739e7 [AVX] Support EXTRACT_SUBVECTOR on x86. This provides a default 
implementation of EXTRACT_SUBVECTOR for x86, going through the stack
in a similr fashion to how the codegen implements BUILD_VECTOR.
Eventually this will get matched to VEXTRACTF128 if AVX is available.

llvm-svn: 124292
 2011-01-26 15:38:49 +00:00
Bruno Cardoso Lopes
2d6bd03b18 fix the encoding and add testcases for ARM nop, yield, wfe and wfi instructions 
llvm-svn: 124288
 2011-01-26 13:28:14 +00:00
Bill Wendling
a4abd1fc4b Add needed braces. 
llvm-svn: 124273
 2011-01-26 02:06:22 +00:00
NAKAMURA Takumi
8ace7260cc Target/X86: Tweak win64's tailcall. 
llvm-svn: 124272
 2011-01-26 02:04:09 +00:00
NAKAMURA Takumi
066378440a Fix whitespace. 
llvm-svn: 124270
 2011-01-26 02:03:37 +00:00
NAKAMURA Takumi
a3d094f248 lib/Target/X86/X86RegisterInfo.cpp: Fix whitespace. 
llvm-svn: 124268
 2011-01-26 01:28:06 +00:00
NAKAMURA Takumi
1557668f7b lib/Target/X86/X86RegisterInfo.cpp: Fix a typo in comment. 
llvm-svn: 124267
 2011-01-26 01:27:58 +00:00
Bill Wendling
69916a2e10 Revert 124230. It was causing test failures. 
llvm-svn: 124233
 2011-01-25 21:48:36 +00:00
Bill Wendling
80dd6f7494 The floating point value is encoded in its binary form as an Imm. Convert it 
appropriately so that it prints out the decimal representation.

llvm-svn: 124230
 2011-01-25 21:27:46 +00:00
Evan Cheng
8e47a6e196 Don't merge restore with tail call instruction. 
llvm-svn: 124167
 2011-01-25 01:28:33 +00:00
Anton Korobeynikov
964b274578 Provide correct registers for EH stuff on ARM 
llvm-svn: 124151
 2011-01-24 22:38:45 +00:00
Chris Lattner
9ba0a83f2b fix a missing shuffle pattern, PR9009. Patch by Artiom Myaskouvskey! 
llvm-svn: 124102
 2011-01-24 03:42:46 +00:00
Chris Lattner
c025bec9e1 this isn't a memset, we do convert dest[i] to one though :) 
llvm-svn: 124097
 2011-01-24 02:32:00 +00:00
Chris Lattner
1f9ed3b437 with recent work, we now optimize this into: 
define i32 @foo(i32 %x) nounwind readnone ssp {
entry:
  %tobool = icmp eq i32 %x, 0
  %tmp5 = select i1 %tobool, i32 2, i32 1
  ret i32 %tmp5
}

llvm-svn: 124091
 2011-01-24 01:12:18 +00:00
Anders Carlsson
ba7114ef4c Add a memset loop that LoopIdiomRecognize doesn't recognize. 
llvm-svn: 124082
 2011-01-23 20:31:00 +00:00
Rafael Espindola
47bc703c55 Initialize MCNoExecStack. 
llvm-svn: 124079
 2011-01-23 18:50:12 +00:00
Rafael Espindola
547873da60 Add support for the --noexecstack option. 
llvm-svn: 124077
 2011-01-23 17:55:27 +00:00
Ted Kremenek
880c19c032 Null initialize a few variables flagged by 
clang's -Wuninitialized-experimental warning.
While these don't look like real bugs, clang's
-Wuninitialized-experimental analysis is stricter
than GCC's, and these fixes have the benefit
of being general nice cleanups.

llvm-svn: 124073
 2011-01-23 17:05:06 +00:00
Rafael Espindola
aefd549139 Delay the creation of eh_frame so that the user can change the defaults. 
Add support for SHT_X86_64_UNWIND.

llvm-svn: 124059
 2011-01-23 05:43:40 +00:00
Rafael Espindola
492ad6ca06 Remove more duplicated code. 
llvm-svn: 124056
 2011-01-23 04:43:11 +00:00
Rafael Espindola
59c1246cee Remove duplicated code. 
llvm-svn: 124054
 2011-01-23 04:28:49 +00:00
Venkatraman Govindaraju
66369057ae Pass sret arguments through the stack instead of through registers in Sparc backend. It makes the code generated more compliant with the sparc32 ABI. 
llvm-svn: 124030
 2011-01-22 13:05:16 +00:00
Venkatraman Govindaraju
3c37c9914f Added ICC, FCC as uses of movcc instruction to generate correct code when -mattr=v9 is used. 
llvm-svn: 124027
 2011-01-22 11:36:24 +00:00
Venkatraman Govindaraju
c20beed917 Sparc backend: 
Rename FLUSH to FLUSHW.
 Output "ta 3" instead of a "flushw" instruction if v8 instruction set is used.

llvm-svn: 123997
 2011-01-21 22:00:00 +00:00
Evan Cheng
0dfe28a9b5 Last round of fixes for movw + movt global address codegen. 
1. Fixed ARM pc adjustment.
2. Fixed dynamic-no-pic codegen
3. CSE of pc-relative load of global addresses.

It's now enabled by default for Darwin.

llvm-svn: 123991
 2011-01-21 18:55:51 +00:00
Bruno Cardoso Lopes
2f96371a7a Fix the encoding of QADD/SUB, QDADD/SUB. While qadd16, qadd8 use "rd, rn, rm", 
qadd and qdadd uses "rd, rm, rn", the same applies to the 'sub' variants. This
is described in ARM manuals and matches the encoding used by the gnu assembler.

llvm-svn: 123975
 2011-01-21 14:07:40 +00:00
Venkatraman Govindaraju
6a083c355b Implement support for byval arguments in Sparc backend. 
llvm-svn: 123974
 2011-01-21 14:00:01 +00:00
Andrew Trick
7155e98904 Convert -enable-sched-cycles and -enable-sched-hazard to -disable 
flags. They are still not enable in this revision.

Added TargetInstrInfo::isZeroCost() to fix a fundamental problem with
the scheduler's model of operand latency in the selection DAG.

Generalized unit tests to work with sched-cycles.

llvm-svn: 123969
 2011-01-21 05:51:33 +00:00
Evan Cheng
52fe62c996 Don't be overly aggressive with CSE of "ldr constantpool". If it's a pc-relative 
value, the "add pc" must be CSE'ed at the same time. We could follow the same
approach as T2 by adding pseudo instructions that combine the ldr + "add pc".
But the better approach is to use movw + movt (which I will enable soon), so
I'll leave this as a TODO.

llvm-svn: 123949
 2011-01-20 23:55:07 +00:00
Bruno Cardoso Lopes
6aeb2e320f Fix the encoding and parsing of clrex instruction 
llvm-svn: 123936
 2011-01-20 19:18:32 +00:00
Bruno Cardoso Lopes
c0f87c11d6 Change instruction names for consistency 
llvm-svn: 123930
 2011-01-20 18:36:07 +00:00
Bruno Cardoso Lopes
5f06c0aa3b Add cdp/cdp2 instructions for thumb/thumb2 
llvm-svn: 123929
 2011-01-20 18:32:09 +00:00
Bruno Cardoso Lopes
3584c02d83 - Use a more appropriate name for Owen's ARM Parser isMCR hack since the same operands can be present 
in cdp/cdp2 instructions. Also increase the hack with cdp/cdp2 instructions.
- Fix the encoding of cdp/cdp2 instructions for ARM (no thumb and thumb2 yet) and add testcases for t
hem.

llvm-svn: 123927
 2011-01-20 18:06:58 +00:00
Bruno Cardoso Lopes
75712e8a7a Add mcr*2 and mr*c2 support to thumb2 targets 
llvm-svn: 123919
 2011-01-20 16:58:48 +00:00
Bruno Cardoso Lopes
f377d1721e Add mcr* and mr*c support to thumb targets 
llvm-svn: 123917
 2011-01-20 16:35:57 +00:00
Kalle Raiskila
070fb5e54d Allow sign-extending of i8 and i16 to i128 on SPU. 
llvm-svn: 123912
 2011-01-20 15:49:06 +00:00
Bruno Cardoso Lopes
0312bb222e Refactor mcr* and mr*c instructions into classes with the same encoding. No functionality change. 
llvm-svn: 123910
 2011-01-20 13:17:59 +00:00
Evan Cheng
d9fdc9771e Correct itinerary entry for t2MOV_pic_ga_add_pc. 
llvm-svn: 123907
 2011-01-20 08:43:03 +00:00