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4130 Commits

Author SHA1 Message Date
Sylvestre Ledru
b77340e506 Revert 'Fix a typo 'iff' => 'if''. iff is an abreviation of if and only if. See: http://en.wikipedia.org/wiki/If_and_only_if Commit 164767 
llvm-svn: 164768
 2012-09-27 10:14:43 +00:00
Sylvestre Ledru
1c5e7904de Fix a typo 'iff' => 'if' 
llvm-svn: 164767
 2012-09-27 09:59:43 +00:00
Chad Rosier
4c89e0343a Rather then have a wrapper function, have tblgen instantiate the implementation. 
Also remove an unused argument.

llvm-svn: 164567
 2012-09-24 22:57:55 +00:00
Chad Rosier
599b467187 Rather then have a wrapper function, have tblgen instantiate the implementation. 
llvm-svn: 164548
 2012-09-24 19:32:29 +00:00
Andrew Trick
7a73f9d7f4 Machine Model (-schedmodel only). Added SchedAliases. 
Allow subtargets to tie SchedReadWrite types to processor specific
sequences or variants.

llvm-svn: 164451
 2012-09-22 02:24:21 +00:00
Chad Rosier
fd5e542cea [ms-inline asm] Expose the mnemonicIsValid() function in the AsmParser. 
llvm-svn: 164420
 2012-09-21 22:21:26 +00:00
Chad Rosier
64fd35f379 Whitespace. 
llvm-svn: 164406
 2012-09-21 19:25:59 +00:00
Dmitri Gribenko
aeecde380d Clarify comment. 
llvm-svn: 164371
 2012-09-21 15:26:34 +00:00
Micah Villmow
cb0e426061 Add in new data types that are used by AMDIL/ANL among others. 
llvm-svn: 164261
 2012-09-19 22:47:07 +00:00
Owen Anderson
76c554cf2a Soften the pattern-can-never-match error in TableGen into a warning. This pattern can be very useful in cases where you want to define a multiclass that covers both commutative and non-commutative operators (say, add and sub). 
llvm-svn: 164256
 2012-09-19 22:15:06 +00:00
Craig Topper
abbf768c15 Remove code for setting the VEX L-bit as a function of operand size from the code emitters and the disassembler table builder. Fix a couple instructions that were still missing VEX_L. 
llvm-svn: 164204
 2012-09-19 06:37:45 +00:00
Andrew Trick
3ed8eed2ed SchedMachineModel: compress the CPU's WriteLatencyTable. 
llvm-svn: 164199
 2012-09-19 04:43:19 +00:00
Sean Silva
a07c612e3e Iterate deterministicaly over ClassInfo*'s 
Fixes an observed instance of nondeterministic TableGen output.

Review by Jakob.

llvm-svn: 164191
 2012-09-19 01:47:03 +00:00
Sean Silva
c291496fe7 Iterate deterministically over register classes 
Fixes an observed instance of nondeterministic TableGen output.

Review by Jakob.

llvm-svn: 164190
 2012-09-19 01:47:01 +00:00
Sean Silva
eedf4ffbcb Refactor Record* by-ID comparator to Record.h 
This is a generally useful utility; there's no reason to have it hidden
in CodeGenDAGPatterns.cpp.

Also, rename it to fit the other comparators in Record.h

Review by Jakob.

llvm-svn: 164189
 2012-09-19 01:47:00 +00:00
Benjamin Kramer
9958678403 FileCheck: Fix off-by-one bug that made CHECK-NOT: ignore the next character after the colon. 
llvm-svn: 164165
 2012-09-18 20:51:39 +00:00
Craig Topper
2c492a1861 Make custom operand parsing mnemonic indices use the same mnemonic table as the match table. Reorder fields in OperandMatchEntry to provide the least amount of padding for in tree targets. 
llvm-svn: 164109
 2012-09-18 07:02:21 +00:00
Craig Topper
c4107aa8c2 Use variable type for index into mnemonic table. Shrinks size of index field on in tree targets. Saving static data space. 
llvm-svn: 164108
 2012-09-18 06:10:45 +00:00
Andrew Trick
6cba50cbb4 Replaced ReInitMCSubtargetInfo with InitMCProcessor. 
Now where we used to call ReInitMCSubtargetInfo, we actually recompute
the same information as InitMCSubtargetInfo instead of only setting
the feature bits.

llvm-svn: 164105
 2012-09-18 05:33:15 +00:00
Andrew Trick
73e100e6f5 comment typo 
llvm-svn: 164097
 2012-09-18 04:03:30 +00:00
Andrew Trick
418db6184f TableGen subtarget emitter. Use getSchedClassIdx. 
llvm-svn: 164096
 2012-09-18 03:55:55 +00:00
Andrew Trick
b7b658d440 TableGen subtarget emitter. Generate resolveSchedClass generated hook for resolving instruction variants. 
llvm-svn: 164095
 2012-09-18 03:41:43 +00:00
Andrew Trick
c2ee4420fd TableGen subtarget emitter. Remove unnecessary header dependence. 
llvm-svn: 164094
 2012-09-18 03:32:57 +00:00
Andrew Trick
65c7aae93f TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine model. 
llvm-svn: 164092
 2012-09-18 03:18:56 +00:00
Craig Topper
24762462b0 Mark asm matcher conversion table as const. 
llvm-svn: 164088
 2012-09-18 01:41:49 +00:00
Craig Topper
5f44668251 Fix typo in comment. No functional change. 
llvm-svn: 164086
 2012-09-18 01:13:36 +00:00
Andrew Trick
2b04a12c0c Backout the wrong subtarget emitter fix 
llvm-svn: 164078
 2012-09-17 23:14:15 +00:00
Andrew Trick
1956ad7efe Fix release build after reverting 
llvm-svn: 164075
 2012-09-17 23:05:04 +00:00
Andrew Trick
150c97940b Revert r164061-r164067. Most of the new subtarget emitter. 
I have to work out the Target/CodeGen header dependencies
before putting this back.

llvm-svn: 164072
 2012-09-17 23:00:42 +00:00
Andrew Trick
9400ee3c79 InitMCProcessor 
llvm-svn: 164066
 2012-09-17 22:19:12 +00:00
Andrew Trick
81e5a058f2 comment typo 
llvm-svn: 164064
 2012-09-17 22:19:04 +00:00
Andrew Trick
22072f5bf2 TableGen subtarget emitter. Use getSchedClassIdx. 
llvm-svn: 164063
 2012-09-17 22:19:01 +00:00
Andrew Trick
7403ff5282 TableGen subtarget emitter. Generate resolveSchedClass generated hook for resolving instruction variants. 
llvm-svn: 164062
 2012-09-17 22:18:58 +00:00
Andrew Trick
8a499d1f62 TableGen subtarget emitter. Initialize MCSubtargetInfo with the new machine model. 
llvm-svn: 164061
 2012-09-17 22:18:55 +00:00
Andrew Trick
f5182127b1 TableGen subtarget emitter. Format and emit data tables for the new machine model. 
llvm-svn: 164060
 2012-09-17 22:18:50 +00:00
Andrew Trick
ef09f46517 TableGen subtarget emitter. Generate data tables for the new machine model. 
Map the CodeGenSchedule object model onto data tables. The structure
of the data tables is defined in MC, so for convenience we include
MCSchedule.h. The alternative is maintaining a redundant copy of the
table structure definitions. Mapping the object model onto data tables
is sufficiently complicated that it should not be interleaved with
emitting source code. This avoids major problem with the backend for
itinerary generation.

llvm-svn: 164059
 2012-09-17 22:18:48 +00:00
Andrew Trick
cf41195b6a TableGen subtarget emitter. Emit processor resources for the new machine model. 
llvm-svn: 164058
 2012-09-17 22:18:45 +00:00
Andrew Trick
d15e58e200 TableGen subtarget parser: Add getProcResourcesIdx(). 
llvm-svn: 164057
 2012-09-17 22:18:43 +00:00
Jim Grosbach
68def8a302 TableGen: Add initializer. 
Keep GCC's warnings happy. It can't reason out that the state machine won't
ever hit the potentially uninitialized use in OPC_FilterValue.

llvm-svn: 164041
 2012-09-17 18:00:53 +00:00
Axel Naumann
bcdf671ac4 Fix a few vars that can end up being used without initialization. 
The cases where no initialization happens should still be checked for logic flaws.

llvm-svn: 164032
 2012-09-17 14:20:57 +00:00
Michael Liao
00438be1a0 Fix typo 
llvm-svn: 164012
 2012-09-17 04:43:39 +00:00
Craig Topper
5e50ef6b15 Add 'virtual' keywoards to output file for overridden functions. 
llvm-svn: 164002
 2012-09-16 18:25:36 +00:00
Craig Topper
f3580aa31e Add 'virtual' keywoards to output file for overridden functions. 
llvm-svn: 163999
 2012-09-16 16:35:22 +00:00
Dmitri Gribenko
dd5d6c0da7 Fix Doxygen issues: wrap code examples in \code and use \p to refer to 
parameters.

llvm-svn: 163984
 2012-09-15 20:22:05 +00:00
Craig Topper
7989d0ccdc Revert r163878 as it breaks on targets with alternate register names. Such targets do not exist in the main tree so this was not noticed. 
llvm-svn: 163959
 2012-09-15 01:22:42 +00:00
Andrew Trick
25c8faee30 TableGen subtarget parser. Handle new machine model. 
Collect processor resources from the subtarget defs.

llvm-svn: 163953
 2012-09-15 00:20:02 +00:00
Andrew Trick
0587f1d794 TableGen subtarget parser. Handle new machine model. 
Infer SchedClasses from variants defined by the target or subtarget.

llvm-svn: 163952
 2012-09-15 00:19:59 +00:00
Andrew Trick
b324ff57ad TableGen subtarget parser. Handle new machine model. 
Collect SchedClasses and SchedRW types from the subtarget defs.

llvm-svn: 163951
 2012-09-15 00:19:57 +00:00
Craig Topper
0320f5eded Allow the second opcode info table to be 8, 16, or 32-bits as needed to represent additional fragments. This recovers some space on ATT X86 syntax and PowerPC which only need 40-bits instead of 48-bits. This also increases ARM to 64-bits to fully encode all of its operands. 
llvm-svn: 163880
 2012-09-14 08:33:11 +00:00
Craig Topper
5cd6b912e7 Reduce size of register name index tables by using uint16_t for all in tree targets. If more than 16-bits are needed for any out of tree targets, code will detect and use uint32_t instead. 
llvm-svn: 163878
 2012-09-14 06:37:49 +00:00