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6 Commits

Author SHA1 Message Date
Chandler Carruth
b9332cb8d7 Update structured references to the license to the new license.
Since these are intended to be short and succinct, I've used the SPDX
full name. It's human readable, but formally agreed upon and will be
part of the SPDX spec for licenses.

llvm-svn: 351649
2019-01-19 11:30:51 +00:00
James Y Knight
2a6af41342 [Sparc] Implement i64 load/store support for 32-bit sparc.
The LDD/STD instructions can load/store a 64bit quantity from/to
memory to/from a consecutive even/odd pair of (32-bit) registers. They
are part of SparcV8, and also present in SparcV9. (Although deprecated
there, as you can store 64bits in one register).

As recommended on llvmdev in the thread "How to enable use of 64bit
load/store for 32bit architecture" from Apr 2015, I've modeled the
64-bit load/store operations as working on a v2i32 type, rather than
making i64 a legal type, but with few legal operations. The latter
does not (currently) work, as there is much code in llvm which assumes
that if i64 is legal, operations like "add" will actually work on it.

The same assumption does not hold for v2i32 -- for vector types, it is
workable to support only load/store, and expand everything else.

This patch:
- Adds a new register class, IntPair, for even/odd pairs of registers.

- Modifies the list of reserved registers, the stack spilling code,
  and register copying code to support the IntPair register class.

- Adds support in AsmParser. (note that in asm text, you write the
  name of the first register of the pair only. So the parser has to
  morph the single register into the equivalent paired register).

- Adds the new instructions themselves (LDD/STD/LDDA/STDA).

- Hooks up the instructions and registers as a vector type v2i32. Adds
  custom legalizer to transform i64 load/stores into v2i32 load/stores
  and bitcasts, so that the new instructions can actually be
  generated, and marks all operations other than load/store on v2i32
  as needing to be expanded.

- Copies the unfortunate SelectInlineAsm hack from ARMISelDAGToDAG.
  This hack undoes the transformation of i64 operands into two
  arbitrarily-allocated separate i32 registers in
  SelectionDAGBuilder. and instead passes them in a single
  IntPair. (Arbitrarily allocated registers are not useful, asm code
  expects to be receiving a pair, which can be passed to ldd/std.)

Also adds a bunch of test cases covering all the bugs I've added along
the way.

Differential Revision: http://reviews.llvm.org/D8713

llvm-svn: 244484
2015-08-10 19:11:39 +00:00
Jim Grosbach
84b2fe36c8 Tidy up. s/Low Level Virtual Machine/LLVM/.
LLVM isn't an acronym anymore.

llvm-svn: 148985
2012-01-25 22:00:23 +00:00
Gabor Greif
63ef2849b2 * llvm.spec.in: update blurb
* autoconf/AutoRegen.sh: use variables for autofoo versions
* autoconf/configure.ac: test for some more functions
                         that are not guaranteed on solaris

Note: the svn:mime-type of autoconf/AutoRegen.sh
      should be set to something that allows for
			text compares using svn diff
llvm-svn: 39800
2007-07-13 09:48:29 +00:00
Reid Spencer
d3c41e4585 Minor technical correction in documentation.
llvm-svn: 29784
2006-08-21 01:58:57 +00:00
Reid Spencer
65d2e70cc5 Transform the LLVM RPM spec file to be a configured file. This allows us
to automatically pick up the configured version number and other details.
Also, update the contents of this script to allow building both a source
and binary version of the RPM package.

llvm-svn: 29716
2006-08-16 00:42:52 +00:00