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1477 Commits

Author SHA1 Message Date
Evan Cheng
43c7084625 Let tblgen only generate fastisel routines, not the class definition. This makes it easier for targets to define its own fastisel class. 
llvm-svn: 55679
 2008-09-03 00:03:49 +00:00
Evan Cheng
9817be2f96 Change getBinaryCodeForInstr prototype. First operand MachineInstr& should be const. Make corresponding changes. 
llvm-svn: 55623
 2008-09-02 06:51:36 +00:00
Owen Anderson
3aa3841da2 Add initial support for fast isel of instructions that have inputs pinned to physical registers. 
llvm-svn: 55545
 2008-08-29 17:45:56 +00:00
Dan Gohman
c7b8401b77 Add a target callback for FastISel. 
llvm-svn: 55512
 2008-08-28 23:21:34 +00:00
Gabor Greif
de8ed9f431 just a brain dump for a small tool 
that brings us to 80-col violations
or tabs.

Usage:
  visit-violations <file>

At the moment it outputs editor invocations.

llvm-svn: 55509
 2008-08-28 23:15:28 +00:00
Gabor Greif
86c795a8ca erect abstraction boundaries for accessing SDValue members, rename Val -> Node to reflect semantics 
llvm-svn: 55504
 2008-08-28 21:40:38 +00:00
Owen Anderson
a5b87bf7e2 Add support for fast-isel of opcodes that require use of extract_subreg. Because of how extract_subreg is treated, it requires special case handling. 
llvm-svn: 55480
 2008-08-28 18:06:12 +00:00
Dan Gohman
378f477a02 Update a comment to reflect recent changes. 
llvm-svn: 55418
 2008-08-27 16:18:22 +00:00
Dan Gohman
5e5f1c9e8f Basic FastISel support for floating-point constants. 
llvm-svn: 55401
 2008-08-27 01:09:54 +00:00
Gabor Greif
4b86114f92 disallow direct access to SDValue::ResNo, provide a getter instead 
llvm-svn: 55394
 2008-08-26 22:36:50 +00:00
Dan Gohman
84d7f86244 Refactor a bunch of FastISelEmitter code into a helper class, and 
put each major step in a separate function. This makes the high
level sequence of events easier to follow.

llvm-svn: 55385
 2008-08-26 21:21:20 +00:00
Cedric Venet
62a65ed510 - small bug corrected: incorrect iterator type. 
- fix to please VS: add a return after an assert.

llvm-svn: 55380
 2008-08-26 19:49:04 +00:00
Owen Anderson
9e2381b77d We need to check that the return type is correct, even in cases where we don't 
have a return type that differs from the operand types.

llvm-svn: 55376
 2008-08-26 18:50:00 +00:00
Chris Lattner
1804f18b34 code simplification, no functionality change. 
llvm-svn: 55363
 2008-08-26 07:01:28 +00:00
Chris Lattner
006fc6636d stabilize more printing, this doesn't cause a problem 
in the example attached to PR2590, but is a problem in general.

llvm-svn: 55361
 2008-08-26 06:50:46 +00:00
Chris Lattner
6adb1b1b26 stablize SubRegsSet printing, part of PR2590 
llvm-svn: 55360
 2008-08-26 06:49:06 +00:00
Chris Lattner
e589d360a1 Stabilize 'getDwarfRegNumFull' output to not depend on random memory 
orders, part of PR2590

llvm-svn: 55359
 2008-08-26 06:43:25 +00:00
Owen Anderson
9c207563a1 Throw the switch to allow FastISel to emit instructions whose return types different from their inputs. Next step: adding lowering pattens in FastISel that actually use these newly available opcodes. 
llvm-svn: 55349
 2008-08-26 01:22:59 +00:00
Owen Anderson
7e677167d6 Enhance TableGen to emit code for FastISel of opcodes with variadic return types without slowing down opcodes that are not variadic. No such opcodes are currently generated, but in theory it should be a matter of just hitting the switch. 
llvm-svn: 55347
 2008-08-26 00:42:26 +00:00
Owen Anderson
9264f41ef2 Add a RetVT parameter to emitted FastISel methods, so that we will be able to pass the desired return 
type down.  This is not currently used.

llvm-svn: 55345
 2008-08-25 23:58:18 +00:00
Owen Anderson
19b73e58e8 Deepen the map structure tablegen uses to compute FastISel patterns, in preparation for having patterns 
with return types that differ from their input types.  This is not yet used.

llvm-svn: 55344
 2008-08-25 23:43:09 +00:00
Owen Anderson
27491bbf2c Add support for fast isel of (integer) immediate materialization pattens, and use them to support 
bitcast of constants in fast isel.

llvm-svn: 55325
 2008-08-25 20:20:32 +00:00
Dan Gohman
a9d5f9b006 Move the point at which FastISel taps into the SelectionDAGISel 
process up to a higher level. This allows FastISel to leverage
more of SelectionDAGISel's infastructure, such as updating Machine
PHI nodes.

Also, implement transitioning from SDISel back to FastISel in
the middle of a block, so it's now possible to go back and
forth. This allows FastISel to hand individual CallInsts and other
complicated things off to SDISel to handle, while handling the rest
of the block itself.

To help support this, reorganize the SelectionDAG class so that it
is allocated once and reused throughout a function, instead of
being completely reallocated for each block.

llvm-svn: 55219
 2008-08-23 02:25:05 +00:00
Dan Gohman
46c93eebcd Add a few comments. 
llvm-svn: 55157
 2008-08-22 00:28:15 +00:00
Dan Gohman
a398d11527 Factor out the predicate check code from DAGISelEmitter.cpp 
and use it in FastISelEmitter.cpp, and make FastISel
subtarget aware. Among other things, this lets it work
properly on x86 targets that don't have SSE, where it
successfully selects x87 instructions.

llvm-svn: 55156
 2008-08-22 00:20:26 +00:00
Dan Gohman
a6e647dd7c Basic fast-isel support for instructions with constant int operands. 
llvm-svn: 55099
 2008-08-21 01:41:07 +00:00
Dan Gohman
e628777073 Remove the code that limited FastISel to certain fixed signatures. 
llvm-svn: 55096
 2008-08-21 00:35:26 +00:00
Dan Gohman
4ab3376173 Begin making more use of the FastISelEmitter class. 
llvm-svn: 55093
 2008-08-21 00:19:05 +00:00
Dan Gohman
d79f723519 Remove an obsolete todo comment. 
llvm-svn: 55080
 2008-08-20 21:47:28 +00:00
Dan Gohman
74bfad70e1 Factor the code for determining the target-specific instruction 
namespace out of the isel emitters and into common code.

llvm-svn: 55079
 2008-08-20 21:45:57 +00:00
Dan Gohman
ddebe95287 Simplify FastISel's constructor argument list, make the FastISel 
class hold a MachineRegisterInfo member, and make the
MachineBasicBlock be passed in to SelectInstructions rather
than the FastISel constructor.

llvm-svn: 55076
 2008-08-20 21:05:57 +00:00
Dan Gohman
ed5e30b819 Fix the string for MVT::isVoid. 
llvm-svn: 55034
 2008-08-20 01:44:30 +00:00
Dan Gohman
ebba5dd8be For now, restrict FastISel to instructions that only involve one 
register class.

llvm-svn: 55008
 2008-08-19 20:58:14 +00:00
Dan Gohman
69eb9fb38e Factor out the code to scan an instruction's operands into a 
helper function.

llvm-svn: 55007
 2008-08-19 20:56:30 +00:00
Dan Gohman
85448ceb8d Add more comments. 
llvm-svn: 55004
 2008-08-19 20:36:33 +00:00
Dan Gohman
b60099089a Fix indentation in FastISel tablegen-emitted code. 
llvm-svn: 55003
 2008-08-19 20:31:38 +00:00
Dan Gohman
a8dfd17e4e Add more checking to filter out more kinds of things that 
FastISel doesn't support yet.

llvm-svn: 55002
 2008-08-19 20:30:54 +00:00
Dan Gohman
1701d4ef7e 80 columns. 
llvm-svn: 54998
 2008-08-19 18:07:49 +00:00
Dan Gohman
3a57ef9668 Add a few doxygen comments. 
llvm-svn: 54997
 2008-08-19 18:06:12 +00:00
Dan Gohman
fbc4410ada Remove an unneeded #include. 
llvm-svn: 54996
 2008-08-19 17:53:16 +00:00
Devang Patel
84b8e5630e Compress manpages. 
llvm-svn: 54971
 2008-08-19 01:17:41 +00:00
Owen Anderson
169e5e5b99 Speed up addRegisterDead by adding more fast checks before performing the expensive 
subregister query, and by increasing the size of the subregister hashtable so
that there are fewer collisions.

llvm-svn: 54781
 2008-08-14 18:34:18 +00:00
Daniel Dunbar
4e592412d4 Update makellvm to return correct result code. 
llvm-svn: 54756
 2008-08-13 20:43:56 +00:00
Dan Gohman
4b1b033f89 Initial checkin of the new "fast" instruction selection support. See 
the comments in FastISelEmitter.cpp for details on what this is.
This is currently experimental and unusable.

llvm-svn: 54751
 2008-08-13 20:19:35 +00:00
Dan Gohman
502d2aebff Oops, check in these files too, for the FastISel -> Fast rename. 
llvm-svn: 54750
 2008-08-13 19:55:00 +00:00
Chris Lattner
fecb2b44a4 remove obsolete files 
llvm-svn: 54630
 2008-08-11 06:12:45 +00:00
Bill Wendling
cff4a97a86 Add ARM to the targets to build. 
llvm-svn: 54386
 2008-08-05 23:52:28 +00:00
Mon P Wang
fb483982f5 Added support for overloading intrinsics (atomics) based on pointers 
to different address spaces.  This alters the naming scheme for those
intrinsics, e.g., atomic.load.add.i32 => atomic.load.add.i32.p0i32

llvm-svn: 54195
 2008-07-30 04:36:53 +00:00
Bill Wendling
3a37809823 Don't build with 4.0. 
llvm-svn: 54137
 2008-07-28 18:45:36 +00:00
Dan Gohman
9742f7772d Rename SDOperand to SDValue. 
llvm-svn: 54128
 2008-07-27 21:46:04 +00:00