Zlatko Buljan
3153f38fd5
[mips][microMIPS] Add CodeGen support for microMIPSr6 ROTR and ROTRV and add tests for LL, SC, SYSCALL, ROTR, ROTRV, LWM32, SWM32 and MOVEP instructions
...
Differential Revision: http://reviews.llvm.org/D19857
llvm-svn: 268491
2016-05-04 12:02:12 +00:00
Simon Atanasyan
226923909e
[Mips] Adjust float ABI settings in case of MIPS16 mode.
...
Hard float for mips16 means essentially to compile as soft float but to
use a runtime library for soft float that is written with native mips32
floating point instructions (those runtime routines run in mips32 hard
float mode).
The patch reviewed by Reed Kotler.
llvm-svn: 195123
2013-11-19 12:20:17 +00:00
Reed Kotler
57455fdc7c
Let rotr and bswap be handled by expansion for Mips16 since we don't
...
have native instructions for this.
llvm-svn: 192207
2013-10-08 17:32:33 +00:00
Akira Hatanaka
fd548b69f5
Change names for MIPS "generic" processors defined in Mips.td to match what GNU
...
tools use. Patch by Simon Atanasyan.
"mips32r1" => "mips32"
"4ke" => mips32r2"
"mips64r1" => "mips64"
llvm-svn: 145451
2011-11-29 23:08:41 +00:00
Akira Hatanaka
5479850400
Remove unnecessary checking of register operands.
...
llvm-svn: 140872
2011-09-30 19:18:24 +00:00
Bruno Cardoso Lopes
93e5c2fb64
Add ROTR and ROTRV mips32 instructions. Patch by Akira Hatanaka
...
llvm-svn: 121377
2010-12-09 17:32:30 +00:00
