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Commit Graph

4046 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
2279c46fe0 Tighten the insert() API for bundled instructions.
The normal insert() function takes an MBB::iterator position, and
inserts a stand-alone MachineInstr as before.

The insert() function that takes an MBB::instr_iterator position can
insert instructions inside a bundle, and will now update the bundle
flags correctly when that happens.

When the insert position is between two bundles, it is unclear whether
the instruction should be appended to the previous bundle, prepended to
the next bundle, or stand on its own. The MBB::insert() function doesn't
bundle the instruction in that case, use the MIBundleBuilder class for
that.

llvm-svn: 170437
2012-12-18 17:54:53 +00:00
Jakob Stoklund Olesen
3f8f107cc8 Tighten up the erase/remove API for bundled instructions.
Most code is oblivious to bundles and uses the MBB::iterator which only
visits whole bundles. MBB::erase() operates on whole bundles at a time
as before.

MBB::remove() now refuses to remove bundled instructions. It is not safe
to remove all instructions in a bundle without deleting them since there
is no way of returning pointers to all the removed instructions.

MBB::remove_instr() and MBB::erase_instr() will now update bundle flags
correctly, lifting individual instructions out of bundles while leaving
the remaining bundle intact.

The MachineInstr convenience functions are updated so

  eraseFromParent() erases a whole bundle as before
  eraseFromBundle() erases a single instruction, leaving the rest of its bundle.
  removeFromParent() refuses to operate on bundled instructions, and
  removeFromBundle() lifts a single instruction out of its bundle.

These functions will no longer accidentally split or coalesce bundles -
bundle flags are updated to preserve the existing bundling, and explicit
bundleWith* / unbundleFrom* functions should be used to change the
instruction bundling.

This API update is still a work in progress. I am going to update APIs
first so they maintain bundle flags automatically when possible. Then
I'll add stricter verification of the bundle flags.

llvm-svn: 170384
2012-12-17 23:55:38 +00:00
Chris Lattner
3c0c7d2f07 fix comment.
llvm-svn: 170155
2012-12-13 22:34:43 +00:00
Patrik Hagglund
bbd72d1bcb Change TargetLowering::getRegClassFor to take an MVT, instead of EVT.
Accordingly, add helper funtions getSimpleValueType (in parallel to
getValueType) in SDValue, SDNode, and TargetLowering.

This is the first, in a series of patches.

This is the second attempt. In the first attempt (r169837), a few
getSimpleVT() were hoisted too far, detected by bootstrap failures.

llvm-svn: 170104
2012-12-13 06:34:11 +00:00
Jakob Stoklund Olesen
fa009e8eff Express prepend and append in terms of a more generic insert().
Also add an MIBundleBuilder constructor that takes an existing bundle.
Together these functions make it possible to add instructions to
existing bundles.

llvm-svn: 170063
2012-12-13 00:59:36 +00:00
Patrik Hagglund
caaedc6ade Revert EVT->MVT changes, r169836-169851, due to buildbot failures.
llvm-svn: 169854
2012-12-11 11:14:33 +00:00
Patrik Hagglund
f45125a118 Change TargetLowering::getTypeForExtArgOrReturn to take and return
MVTs, instead of EVTs.

Accordingly, add bitsLT (and similar) to MVT.

llvm-svn: 169850
2012-12-11 10:20:51 +00:00
Patrik Hagglund
758f9c5011 Change TargetLowering::getRegClassFor to take an MVT, instead of EVT.
Accordingly, add helper funtions getSimpleValueType (in parallel to
getValueType) in SDValue, SDNode, and TargetLowering.

This is the first, in a series of patches.

llvm-svn: 169837
2012-12-11 09:10:33 +00:00
Chad Rosier
0b2e4a1ba8 Fall back to the selection dag isel to select tail calls.
This shouldn't affect codegen for -O0 compiles as tail call markers are not
emitted in unoptimized compiles.  Testing with the external/internal nightly
test suite reveals no change in compile time performance.  Testing with -O1,
-O2 and -O3 with fast-isel enabled did not cause any compile-time or
execution-time failures.  All tests were performed on my x86 machine.
I'll monitor our arm testers to ensure no regressions occur there.

In an upcoming clang patch I will be marking the objc_autoreleaseReturnValue
and objc_retainAutoreleaseReturnValue as tail calls unconditionally.  While
it's theoretically true that this is just an optimization, it's an
optimization that we very much want to happen even at -O0, or else ARC
applications become substantially harder to debug.

Part of rdar://12553082

llvm-svn: 169796
2012-12-11 00:18:02 +00:00
Jakob Stoklund Olesen
4bac7884c3 Add an MIBundleBuilder class.
Like the MachineInstrBuilder, this class makes it easier to build
bundles of MachineInstrs.

llvm-svn: 169584
2012-12-07 04:23:35 +00:00
Jakob Stoklund Olesen
1386769d53 Add higher-level API for dealing with bundled MachineInstrs.
This is still a work in progress. The purpose is to make bundling and
unbundling operations explicit, and to catch errors where bundles are
broken or created inadvertently.

The old IsInsideBundle flag is replaced by two MI flags: BundledPred
which has the same meaning as IsInsideBundle, and BundledSucc which is
set on instructions that are bundled with a successor. Having two flags
provdes redundancy to detect when a bundle is inadvertently torn by a
splice() or insert(), and it makes it possible to write bundle iterators
that don't need to peek at adjacent instructions.

The new flags can't be manipulated directly (once setIsInsideBundle is
gone). Instead there are MI functions to make and break bundle bonds.

The setIsInsideBundle function will be removed in a future commit. It
should be replaced by bundleWithPred().

llvm-svn: 169583
2012-12-07 04:23:29 +00:00
Andrew Trick
1a2b4ddd59 RegPressureTracker::dump(): Remove unnecessary argument.
llvm-svn: 169443
2012-12-05 23:05:22 +00:00
Andrew Trick
4360a22194 RegisterPressureTracker: unify virtual registers and physical regunits.
Now that live register units are tracked individually, the code can be simplified.

llvm-svn: 169426
2012-12-05 21:37:47 +00:00
Andrew Trick
67c084b14c RegisterPresssureTracker: Track live physical register by unit.
This is much simpler to reason about, more efficient, and
fixes some corner cases involving implicit super-register defs.
Fixed rdar://12797931.

llvm-svn: 169425
2012-12-05 21:37:42 +00:00
Jakob Stoklund Olesen
75ccdbb1dc Remove unused MachineInstr constructors.
A MachineInstr can only ever be constructed by CreateMachineInstr() and
CloneMachineInstr(), and those factories don't use the removed
constructors.

llvm-svn: 169395
2012-12-05 18:27:39 +00:00
Pedro Artigas
cd715362f7 - Added calls to doInitialization/doFinalization to immutable passes
- fixed ordering of calls to doFinalization to be the reverse of the pass run order due to potential dependencies
- fixed machine module info to operate in the doInitialization/doFinalization model, also fixes some FIXMEs

reviewed by Evan Cheng <evan.cheng@apple.com>

llvm-svn: 169391
2012-12-05 17:12:22 +00:00
Andrew Trick
7da96db06b Added RegisterPressureTracker::dump() for debugging.
llvm-svn: 169359
2012-12-05 06:47:08 +00:00
Manman Ren
40ba054405 Stack Alignment: when creating stack objects in MachineFrameInfo, make sure
the alignment is clamped to TargetFrameLowering.getStackAlignment if the target
does not support stack realignment or the option "realign-stack" is off.

This will cause miscompile if the address is treated as aligned and add is
replaced with or in DAGCombine.

Added a bool StackRealignable to TargetFrameLowering to check whether stack
realignment is implemented for the target. Also added a bool RealignOption
to MachineFrameInfo to check whether the option "realign-stack" is on.

rdar://12713765

llvm-svn: 169197
2012-12-04 00:52:33 +00:00
Jakob Stoklund Olesen
305fb6fe6c Remove VirtRegMap::getRegAllocPref().
Now that there can be multiple hint registers from targets, it doesn't
make sense to have a function that returns 'the' preferred register.

llvm-svn: 169190
2012-12-04 00:35:59 +00:00
Jakob Stoklund Olesen
d099763751 Use MRI::getSimpleHint() instead of getRegAllocPref() in remaining cases.
Targets can provide multiple hints now, so getRegAllocPref() doesn't
make sense any longer because it only returns one preferred register.
Replace it with getSimpleHint() in the remaining heuristics. This
function only

llvm-svn: 169188
2012-12-04 00:30:22 +00:00
Manman Ren
4c21a13abd Stack Alignment: move functions from header file MachineFrameInfo.h.
No functional change for this commit. The follow-up patch will add more stuff to
these functions.

rdar://12713765

llvm-svn: 169186
2012-12-04 00:26:44 +00:00
Jakob Stoklund Olesen
753c5da13c Add VirtRegMap::hasKnownPreference().
Virtual registers with a known preferred register are prioritized by
RAGreedy. This function makes the condition explicit without depending
on getRegAllocPref().

llvm-svn: 169179
2012-12-03 23:23:50 +00:00
Pedro Artigas
80c84a9de4 moves doInitialization and doFinalization to the Pass class and removes some unreachable code in MachineModuleInfo
reviewed by Evan Cheng <evan.cheng@apple.com>

llvm-svn: 169164
2012-12-03 21:56:57 +00:00
Chandler Carruth
ca305491f6 Sort the #include lines for the include/... tree with the script.
AKA: Recompile *ALL* the source code!

This one went much better. No manual edits here. I spot-checked for
silliness and grep-checked for really broken edits and everything seemed
good. It all still compiles. Yell if you see something that looks goofy.

llvm-svn: 169133
2012-12-03 17:02:12 +00:00
Chandler Carruth
a490793037 Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.

Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]

llvm-svn: 169131
2012-12-03 16:50:05 +00:00
Andrew Trick
33aa915f94 misched: Fix RegisterPressureTracker handling of DebugVals.
Assertion failed: (TopRPTracker.getPos() == RegionBegin && "bad initial Top tracker").
rdar://12790302.

llvm-svn: 169072
2012-12-01 01:22:49 +00:00
Bill Wendling
2a966eebb7 Replace r168930 with a more reasonable patch.
The original patch removed a bunch of code that the SjLjEHPrepare pass placed
into the entry block if all of the landing pads were removed during the
CodeGenPrepare class. The more natural way of doing things is to run the CGP
*before* we run the SjLjEHPrepare pass.

Make it so!

llvm-svn: 169044
2012-11-30 22:08:55 +00:00
Pedro Artigas
a84c753671 One more step towards making doInitialization and doFinalization useful for
start up and clean up module passes, now that ASAN and TSAN are fixed the
tests pass

llvm-svn: 168905
2012-11-29 17:47:05 +00:00
Jakob Stoklund Olesen
9bbaa29b20 Use MCPhysReg for RegisterClassInfo allocation orders.
This saves a bit of memory.

llvm-svn: 168852
2012-11-29 03:34:17 +00:00
Jakob Stoklund Olesen
5367ea889f Make the LiveRegMatrix analysis available to targets.
No functional change, just moved header files.

Targets can inject custom passes between register allocation and
rewriting. This makes it possible to tweak the register allocation
before rewriting, using the full global interference checking available
from LiveRegMatrix.

llvm-svn: 168806
2012-11-28 19:13:06 +00:00
Andrew Trick
ceeb35bbb8 misched: Analysis that partitions the DAG into subtrees.
This is a simple, cheap infrastructure for analyzing the shape of a
DAG. It recognizes uniform DAGs that take the shape of bottom-up
subtrees, such as the included matrix multiplication example. This is
useful for heuristics that balance register pressure with ILP. Two
canonical expressions of the heuristic are implemented in scheduling
modes: -misched-ilpmin and -misched-ilpmax.

llvm-svn: 168773
2012-11-28 05:13:28 +00:00
Andrew Trick
98bb349721 misched: rename ScheduleDAGILP to ScheduleDFS to prepare for other heuristics.
llvm-svn: 168772
2012-11-28 05:13:24 +00:00
NAKAMURA Takumi
4504b63c0e llvm/CodeGen: Remove empty files in r168659.
llvm-svn: 168663
2012-11-27 01:21:50 +00:00
Jakub Staszak
231d1e55d4 Remove unused MachineLoopRanges analysis.
llvm-svn: 168659
2012-11-27 01:14:34 +00:00
Owen Anderson
ef8881a314 Revert r168635 "Step towards implementation of pass manager with doInitialization and doFinalization per module detangled from runOn?? calls, still has temporary code not to break ASAN to be removed when that pass conforms to the proposed model".
It appears to have broken at least one buildbot.

llvm-svn: 168654
2012-11-27 00:53:24 +00:00
Owen Anderson
4f32762479 Step towards implementation of pass manager with doInitialization and doFinalization per module detangled from runOn?? calls, still has temporary code not to break ASAN to be removed when that pass conforms to the proposed model
Patch by Pedro Artigas, with feedback from by Chandler Carruth.

llvm-svn: 168635
2012-11-26 23:54:47 +00:00
Chandler Carruth
f6c8834e87 Fix a place where the declaration didn't use LLVM_ENABLE_DUMP but the
definition did.

The last part of PR14324.

llvm-svn: 168363
2012-11-20 10:23:50 +00:00
Tim Northover
3556e52a02 Fix physical register liveness calculations:
+ Take account of clobbers
+ Give outputs priority over inputs since they happen later.

llvm-svn: 168360
2012-11-20 09:56:11 +00:00
Chad Rosier
5bb777b447 [reg scavenger] Fix the isUsed/isAliasUsed functions so as to not report a false
positive.

In this particular case, R6 was being spilled by the register scavenger when it
was in fact dead.  The isUsed function reported R6 as used because the R6_R7
alias was reserved (due to the fact that we've reserved R7 as the FP).  The
solution is to only check if the original register (i.e., R6) isReserved and
not the aliases.  The aliases are only checked to make sure they're available.

The test case is derived from one of the nightly tester benchmarks and is rather
intractable and difficult to reproduce, so I haven't included it.
rdar://12592448

llvm-svn: 168054
2012-11-15 18:13:20 +00:00
Dmitri Gribenko
610d06f00e Use empty parens for empty function parameter list instead of '(void)'.
llvm-svn: 168049
2012-11-15 16:51:49 +00:00
Anton Korobeynikov
980253fa36 Fix comment
llvm-svn: 167947
2012-11-14 19:17:44 +00:00
Anton Korobeynikov
3edf77ac04 Use TARGET2 relocation for TType references on ARM.
Do some cleanup of the code while here.

Inspired by patch by Logan Chien!

llvm-svn: 167904
2012-11-14 01:47:00 +00:00
Andrew Trick
ce37595f51 misched: Don't consider artificial edges weak edges.
For now be more conservative in case other out-of-tree schedulers rely
on the old behavior of artificial edges.

llvm-svn: 167808
2012-11-13 02:35:06 +00:00
Andrew Trick
7f7b5f4787 misched: Target-independent support for load/store clustering.
This infrastructure is generally useful for any target that wants to
strongly prefer two instructions to be adjacent after scheduling.

A following checkin will add target-specific hooks with unit
tests. Then this feature will be enabled by default with misched.

llvm-svn: 167742
2012-11-12 19:40:10 +00:00
Andrew Trick
ad4b55b3d8 misched: Infrastructure for weak DAG edges.
This adds support for weak DAG edges to the general scheduling
infrastructure in preparation for MachineScheduler support for
heuristics based on weak edges.

llvm-svn: 167738
2012-11-12 19:28:57 +00:00
Andrew Trick
8b72906a53 misched: Heuristics based on the machine model.
misched is disabled by default. With -enable-misched, these heuristics
balance the schedule to simultaneously avoid saturating processor
resources, expose ILP, and minimize register pressure. I've been
analyzing the performance of these heuristics on everything in the
llvm test suite in addition to a few other benchmarks. I would like
each heuristic check to be verified by a unit test, but I'm still
trying to figure out the best way to do that. The heuristics are still
in considerable flux, but as they are refined we should be rigorous
about unit testing the improvements.

llvm-svn: 167527
2012-11-07 07:05:09 +00:00
Andrew Trick
036d5e0f06 misched: handle on-the-fly regpressure queries better for 2-addr
instructions without relying on liveintervals.

llvm-svn: 167526
2012-11-07 07:05:05 +00:00
Andrew Trick
dd9dff5d77 misched: TargetSchedule interface for machine resources.
Expose the processor resources defined by the machine model to the
scheduler and other clients through the TargetSchedule interface.

Normalize each resource count with respect to other kinds of
resources. This allows scheduling heuristics to balance resources
against other kinds of resources and latency.

llvm-svn: 167444
2012-11-06 07:10:38 +00:00
Andrew Trick
76ebc86f9a ScheduleDAG interface. Added OrderKind to distinguish nonregister dependencies.
This is in preparation for adding "weak" DAG edges, but generally
simplifies the design.

llvm-svn: 167435
2012-11-06 03:13:46 +00:00
Rafael Espindola
79781084a5 Add extra declarations of hash_value needed to build llvm with xlc 12.1.
Patch by Kai!

llvm-svn: 167085
2012-10-31 00:46:18 +00:00