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Commit Graph

21 Commits

Author SHA1 Message Date
Bill Wendling
a472e7be70 Add encoding for ARM "trap" instruction.
llvm-svn: 119938
2010-11-21 11:05:29 +00:00
Jim Grosbach
7de028efd2 Add a CMP test.
llvm-svn: 117187
2010-10-22 23:48:01 +00:00
Jim Grosbach
de52e11864 tidy up.
llvm-svn: 117166
2010-10-22 22:15:48 +00:00
Jim Grosbach
bba77cca02 ARM mode encoding information for CLZ, RBIT, REV*, and PKH*.
llvm-svn: 117165
2010-10-22 22:12:16 +00:00
Jim Grosbach
10195e9b73 Add the encoding information for the rest of the ARM mode multiply instructions.
llvm-svn: 117133
2010-10-22 19:15:30 +00:00
Jim Grosbach
ca2897a0ca More ARM multiply instuction binary encodings.
llvm-svn: 117121
2010-10-22 18:35:16 +00:00
Jim Grosbach
0ae6bf8095 More ARM multiply instruction encoding information.
llvm-svn: 117108
2010-10-22 17:16:17 +00:00
Jim Grosbach
7c42142b71 ARM binary encodings for MVN variants.
llvm-svn: 117076
2010-10-21 22:19:32 +00:00
Jim Grosbach
cb41e97b5c ARM Binary encoding information for BFC/BFI instructions.
llvm-svn: 117072
2010-10-21 22:03:21 +00:00
Jim Grosbach
67f94c42d8 ARM mode encoding information for UBFX and SBFX instructions.
llvm-svn: 116588
2010-10-15 17:15:16 +00:00
Jim Grosbach
608e4fd221 Simplify test file a bit.
llvm-svn: 116540
2010-10-14 23:32:44 +00:00
Jim Grosbach
26842cb893 Add testcase for RRX and ASRS (which effectively tests MOVs, since those
are just forms of that instruction).

llvm-svn: 116538
2010-10-14 23:29:18 +00:00
Jim Grosbach
73c78f8790 MOVi16 and MOVT ARM mode encodings.
llvm-svn: 116498
2010-10-14 18:54:27 +00:00
Jim Grosbach
8f0bea85bf Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions.
llvm-svn: 116421
2010-10-13 19:56:10 +00:00
Jim Grosbach
9c4a598ef2 Add ARM mode operand encoding information for ADDE/SUBE instructions.
llvm-svn: 116412
2010-10-13 18:00:52 +00:00
Jim Grosbach
3fe0337063 Add ARM encoding information for comparisons, forced-cc-out arithmetics, and
arithmetic-with-carry-in instructions.

llvm-svn: 116384
2010-10-13 00:50:27 +00:00
Jim Grosbach
0038f2eec6 Be nitpicky and line up the comments.
llvm-svn: 116365
2010-10-12 23:14:03 +00:00
Jim Grosbach
10d9bbe0ca Add encoding information for the remainder of the generic arithmetic
ARM instructions.

llvm-svn: 116313
2010-10-12 17:11:26 +00:00
Jim Grosbach
29ef87e765 MC machine encoding for simple aritmetic instructions that use a shifted
register operand.

llvm-svn: 116259
2010-10-11 23:16:21 +00:00
Jim Grosbach
3075d28c15 Implement a few more binary encoding bits. Still very early stage proof-of-
concept level stuff at this point, but it is generally working for those
instructions that know how to map the operands.

This patch fills in the register operands for add/sub/or/etc instructions
and adds the conditional execution predicate encoding.

llvm-svn: 116112
2010-10-08 21:45:55 +00:00
Jim Grosbach
edbbf33203 Add test file for simple ARM binary encodings with MC
llvm-svn: 116024
2010-10-08 00:47:59 +00:00