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Commit Graph

209171 Commits

Author SHA1 Message Date
Florian Hahn
22dcffd655 [VPlan] Keep start value in VPWidenIntOrFpInductionRecipe (NFC).
This patch updates VPWidenIntOrFpInductionRecipe to hold the start value
for the induction variable. This makes the start value explicit and
allows for adjusting the start value for a VPlan.

The flexibility will be used in further patches.

Reviewed By: Ayal

Differential Revision: https://reviews.llvm.org/D92129
2021-01-06 11:47:33 +00:00
Sander de Smalen
0dd29f6538 [AArch64][SVE] Emit DWARF location expr for SVE (dbg.declare)
When using dbg.declare, the debug-info is generated from a list of
locals rather than through DBG_VALUE instructions in the MIR.
This patch is different from D90020 because it emits the DWARF
location expressions from that list of locals directly.

Reviewed By: jmorse

Differential Revision: https://reviews.llvm.org/D90044
2021-01-06 11:45:05 +00:00
Fraser Cormack
cc393246a7 [ValueTypes] Fix formatting on scalable vector warning (NFC) 2021-01-06 11:27:44 +00:00
Sander de Smalen
bccf0ebdc1 [LiveDebugValues] Handle spill locations with a fixed and scalable component.
This patch fixes the two LiveDebugValues implementations
(InstrRef/VarLoc)Based to handle cases where the StackOffset contains
both a fixed and scalable component.

This depends on the `TargetRegisterInfo::prependOffsetExpression` being
added in D90020. Feel free to leave comments on that patch if you have them.

Reviewed By: djtodoro, jmorse

Differential Revision: https://reviews.llvm.org/D90046
2021-01-06 11:30:13 +00:00
David Green
6e066a74ee [ARM] Handle any extend whilst lowering addw/addl/subw/subl
Same as a9b6440edd, use zanyext to treat any_extends as zero extends
during lowering to create addw/addl/subw/subl nodes.

Differential Revision: https://reviews.llvm.org/D93835
2021-01-06 11:26:39 +00:00
Florian Hahn
ff9300b791 [VPlan] Add getLiveInIRValue accessor to VPValue.
This patch adds a new getLiveInIRValue accessor to VPValue, which
returns the underlying value, if the VPValue is defined outside of
VPlan. This is required to handle scalars in VPTransformState, which
requires dealing with scalars defined outside of VPlan.

We can simply check VPValue::Def to determine if the value is defined
inside a VPlan.

Reviewed By: Ayal

Differential Revision: https://reviews.llvm.org/D92281
2021-01-06 11:20:42 +00:00
Ben Shi
d602a70113 [RISCV][NFC] Add new test cases for mul 2021-01-06 18:55:56 +08:00
David Green
83152a3449 [ARM] Handle any extend whilst lowering mull
Similar to 78d8a821e23e but for ARM, this handles any_extend whilst
creating MULL nodes, treating them as zextends.

Differential Revision: https://reviews.llvm.org/D93834
2021-01-06 10:51:12 +00:00
Florian Hahn
56cad26119 [VPlan] Use public VPValue constructor in VPPRedInstPHIRecipe (NFC).
VPPredInstPHIRecipe does not need access to VPValue via friendship. It
can just use the public constructor,

Discussed as part of D92281.
2021-01-06 10:47:09 +00:00
Sander de Smalen
33c363bd98 Fix test failure in a7e3339f3b0eb71e43d44e6f59cc8db6a7b110bf
Set the target-triple to aarch64 in debug-info-sve-dbg-value.mir
to avoid "'+sve' is not a recognized feature for this target"
diagnostic.
2021-01-06 10:43:48 +00:00
David Green
0ce85618c7 [AArch64] Handle any extend whilst lowering addw/addl/subw/subl
This adds an extra tablegen PatFrag, zanyext, which matches either any
extend or zext and uses that in the aarch64 backend to handle any
extends in addw/addl/subw/subl patterns.

Differential Revision: https://reviews.llvm.org/D93833
2021-01-06 10:35:23 +00:00
David Green
d0a1eeec50 [AArch64] Handle any extend whilst lowering mull
Demanded bits may turn a sext or zext into an anyext if the top bits are
not needed. This currently prevents the lowering to instructions like
mull, addl and addw. This patch fixes the mull generation by keeping it
simple and treating them like zextends.

Differential Revision: https://reviews.llvm.org/D93832
2021-01-06 10:08:43 +00:00
Sander de Smalen
ba42c87c0b [AArch64][SVE] Emit DWARF location expression for SVE stack objects.
Extend PEI to emit a DWARF expression for StackOffsets that have
a fixed and scalable component. This means the expression that needs
to be added is either:
  <base> + offset
or:
  <base> + offset + scalable_offset * scalereg

where for SVE, the scale reg is the Vector Granule Dwarf register, which
encodes the number of 64bit 'granules' in an SVE vector and which
the debugger can evaluate at runtime.

Reviewed By: jmorse

Differential Revision: https://reviews.llvm.org/D90020
2021-01-06 09:40:53 +00:00
Sander de Smalen
9a270624d8 [AArch64] Use faddp to implement fadd reductions.
Custom-expand legal VECREDUCE_FADD SDNodes
to benefit from pair-wise faddp instructions.

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D59259
2021-01-06 09:36:51 +00:00
Sam Clegg
5b223dea44 [MC][WebAssembly] Avoid recalculating indexes in -gsplit-dwarf mode
Be consistent about asserting before setting WasmIndices.  Adding
these assertions revealed that we were duplicating a lot of work
and setting these indexed twice when running in DWO mode.

Differential Revision: https://reviews.llvm.org/D93650
2021-01-06 01:35:06 -08:00
Fraser Cormack
c1b05d91cf [RISCV] Add vector integer mul/mulh/div/rem ISel patterns
There is no test coverage for the mulhs or mulhu patterns as I can't get
the DAGCombiner to generate them for scalable vectors. There are a few
places in that still need updating for that to work. I left the patterns
in regardless as they are correct.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D94073
2021-01-06 09:24:07 +00:00
Kazu Hirata
cac304a74c [llvm] Use llvm::lower_bound and llvm::upper_bound (NFC) 2021-01-05 21:15:59 -08:00
Kazu Hirata
d5846298bc [MachineSink] Construct SmallVector with iterator ranges (NFC) 2021-01-05 21:15:57 -08:00
Kazu Hirata
b753882cc3 [tools] Use llvm::append_range (NFC) 2021-01-05 21:15:56 -08:00
Christudasan Devadasan
f0d6cc1d99 [GlobalISel] Base implementation for sret demotion.
If the return values can't be lowered to registers
SelectionDAG performs the sret demotion. This patch
contains the basic implementation for the same in
the GlobalISel pipeline.

Furthermore, targets should bring relevant changes
during lowerFormalArguments, lowerReturn and
lowerCall to make use of this feature.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D92953
2021-01-06 10:30:50 +05:30
Mircea Trofin
a3c9c60e8f [NFC] Removed unused prefixes in CodeGen/AMDGPU
This covers the tests starting with h-k.

Differential Revision: https://reviews.llvm.org/D94147
2021-01-05 20:22:40 -08:00
Mircea Trofin
b47fe88605 [NFC] Removed unused prefixes in test/CodeGen/AMDGPU
More patches to follow. This covers the pertinent tests starting with e,
f, and g.

Differential Revision: https://reviews.llvm.org/D94124
2021-01-05 19:18:30 -08:00
Juneyoung Lee
691497c4e5 [Constant] Add containsPoisonElement
This patch

- Adds containsPoisonElement that checks existence of poison in constant vector elements,
- Renames containsUndefElement to containsUndefOrPoisonElement to clarify its behavior & updates its uses properly

With this patch, isGuaranteedNotToBeUndefOrPoison's tests w.r.t constant vectors are added because its analysis is improved.

Thanks!

Reviewed By: nikic

Differential Revision: https://reviews.llvm.org/D94053
2021-01-06 12:10:33 +09:00
Juneyoung Lee
a3da92d4e3 [X86] Update X86InstCombineIntrinsic to use CreateShuffleVector with one vector
This patch updates X86InstCombineIntrinsic.cpp to use the newly updated CreateShuffleVector.

The tests are updated because the updated CreateShuffleVector uses poison value for the second vector.
If I didn't miss something, the masks in the tests are choosing elements from the first vector only; therefore the tests are having equivalent behavior.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D94059
2021-01-06 11:42:45 +09:00
Juneyoung Lee
982327f66d [SLP,LV] Use poison constant vector for shufflevector/initial insertelement
This patch makes SLP and LV emit operations with initial vectors set to poison constant instead of undef.
This is a part of efforts for using poison vector instead of undef to represent "doesn't care" vector.
The goal is to make nice shufflevector optimizations valid that is currently incorrect due to the tricky interaction between undef and poison (see https://bugs.llvm.org/show_bug.cgi?id=44185 ).

Reviewed By: fhahn

Differential Revision: https://reviews.llvm.org/D94061
2021-01-06 11:22:50 +09:00
Reid Kleckner
692055fae7 Suppress GCC Wdangling-else warning on gtest macros
See https://github.com/google/googletest/issues/1119
2021-01-05 17:32:56 -08:00
David Blaikie
b2e950c063 DebugInfo: Add support for always using ranges (rather than low/high pc) in DWARFv5
Given the ability provided by DWARFv5 rnglists to reuse addresses in the
address pool, it can be advantageous to object file size to use range
encodings even when the range could be described by a direct low/high
pc.

Add a flag to allow enabling this in DWARFv5 for the purpose of
experimentation/data gathering.

It might be that it makes sense to enable this functionality by default
for DWARFv5 + Split DWARF at least, where the tradeoff/desire to
optimize for .o file size is more explicit and .o bytes are higher
priority than .dwo bytes.
2021-01-05 16:36:22 -08:00
Roman Lebedev
1f90fe3fab [SimplifyCFG] SimplifyEqualityComparisonWithOnlyPredecessor(): really don't delete DomTree edges multiple times 2021-01-06 01:52:39 +03:00
Roman Lebedev
277b3f26e6 [NFC][SimplifyCFG] Add a test where SimplifyEqualityComparisonWithOnlyPredecessor() deletes existing edge 2021-01-06 01:52:39 +03:00
Roman Lebedev
b91c7be0d6 [SimplifyCFG] SwitchToLookupTable(): switch to non-permissive DomTree updates
... which requires not deleting a DomTree edge that we just deleted.
2021-01-06 01:52:38 +03:00
Roman Lebedev
6af4242547 [NFC][SimplifyCFG] SwitchToLookupTable(): pull out SI->getParent() into a variable 2021-01-06 01:52:38 +03:00
Roman Lebedev
3a3d13f351 [SimplifyCFG] FoldValueComparisonIntoPredecessors(): deal with each predecessor only once
If the predecessor is a switch, and BB is not the default destination,
multiple cases could have the same destination. and it doesn't
make sense to re-process the predecessor, because we won't make any changes,
once is enough.

I'm not sure this can be really tested, other than via the assertion
being added here, which fires without the fix.
2021-01-06 01:52:37 +03:00
Roman Lebedev
8e9041bd74 [SimplifyCFG] FoldValueComparisonIntoPredecessors(): switch to non-permissive DomTree updates
... which requires not adding a DomTree edge that we just added.
2021-01-06 01:52:37 +03:00
Roman Lebedev
a1833b3e90 [SimplifyCFG] simplifyUnreachable(): fix handling of degenerate same-destination conditional branch
One would hope that it would have been already canonicalized into an
unconditional branch, but that isn't really guaranteed to happen
with SimplifyCFG's visitation order.
2021-01-06 01:52:36 +03:00
Roman Lebedev
3fedc10090 [NFC][SimplifyCFG] Add a test with same-destination condidional branch
Reported by Mikael Holmén as post-commit feedback on
https://reviews.llvm.org/rG2d07414ee5f74a09fb89723b4a9bb0818bdc2e18#968162
2021-01-06 01:52:36 +03:00
Roman Lebedev
5341fe1751 [SimplifyCFG] simplifyUnreachable(): switch to non-permissive DomTree updates
... which requires not removing a DomTree edge if the switch's default
still points at that destination, because it can't be removed;
... and not processing the same predecessor more than once.
2021-01-06 01:52:36 +03:00
Changpeng Fang
ff7f88a27c AMDGPU: Annotate amdgpu.noclobber for global loads only
Summary:
  This is to avoid unnecessary analysis since amdgpu.noclobber is only used for globals.

Reviewers:
  arsenm

Fixes:
   SWDEV-239161

Differential Revision:
  https://reviews.llvm.org/D94107
2021-01-05 14:47:19 -08:00
Sanjay Patel
9893ad0999 [SLP] reduce code for finding reduction costs; NFC
We can get both (vector/scalar) costs in a single switch
instead of sequentially.
2021-01-05 17:35:54 -05:00
Mircea Trofin
0f25221f48 [NFC] Removed unused prefixes in test/CodeGen/AMDGPU
More patches to follow.

Differential Revision: https://reviews.llvm.org/D94121
2021-01-05 14:16:52 -08:00
Mircea Trofin
ccfdf4cfae [NFC] Removed unused prefixes in CodeGen/AMDGPU
This is part of the pertinent tests, more to follow in subsequent
patches.

Differential Revision: https://reviews.llvm.org/D94114
2021-01-05 14:10:03 -08:00
Arthur Eubanks
11d7aba210 [FuncAttrs] Infer noreturn
A function is noreturn if all blocks terminating with a ReturnInst
contain a call to a noreturn function. Skip looking at naked functions
since there may be asm that returns.

This can be further refined in the future by checking unreachable blocks
and taking into account recursion. It looks like the attributor pass
does this, but that is not yet enabled by default.

This seems to help with code size under the new PM since PruneEH does
not run under the new PM, missing opportunities to mark some functions
noreturn, which in turn doesn't allow simplifycfg to clean up dead code.
https://bugs.llvm.org/show_bug.cgi?id=46858.

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D93946
2021-01-05 13:25:42 -08:00
Mircea Trofin
5061b97fec [NFC] Removed unused prefixes in CodeGen/AMDGPU/GlobalISel
Differential Revision: https://reviews.llvm.org/D94099
2021-01-05 12:57:17 -08:00
Kazu Hirata
648dfc8cb2 [Inliner] Compute the full cost for the cost benefit analsysis
This patch teaches the inliner to compute the full cost for a call
site where the newly introduced cost benefit analysis is enabled.

Note that the cost benefit analysis requires the full cost to be
computed.  However, without this patch or the -inline-cost-full
option, the early termination logic would kick in when the cost
exceeds the threshold, so we don't get to perform the cost benefit
analysis.  For this reason, we would need to specify four clang
options:

  -mllvm -inline-cost-full
  -mllvm -inline-enable-cost-benefit-analysis

This patch eliminates the need to specify -inline-cost-full.

Differential Revision: https://reviews.llvm.org/D93658
2021-01-05 12:48:49 -08:00
Craig Topper
99bc1220c8 [DAGCombiner] Don't speculatively create an all ones constant in visitREM that might not be used.
This looks to have been done to save some duplicated code under
two different if statements, but it ends up being harmful to D94073.
This speculative constant can be called on a scalable vector type
with i64 element size when i64 scalars aren't legal. The code tries
and fails to find a vector type with i32 elements that it can use.

So only create the node when we know it will be used.
2021-01-05 12:45:57 -08:00
Sanjay Patel
b532dcefa1 [SLP] use reduction kind's opcode for cost model queries; NFC
This should be no-functional-change because the reduction kind
opcodes are 1-for-1 mappings to the instructions we are matching
as reductions. But we want to remove the need for the
`OperationData` opcode field because that does not work when
we start matching intrinsics (eg, maxnum) as reduction candidates.
2021-01-05 15:12:40 -05:00
Sanjay Patel
305c130e7c [SLP] reduce code duplication; NFC 2021-01-05 15:12:40 -05:00
Krzysztof Parzyszek
1dc8dfc8bb [Hexagon] Silence unused function warning with gcc10, NFC 2021-01-05 14:11:45 -06:00
Whitney Tsang
4264937ee8 [LoopNest] Remove unused include.
Differential Revision: https://reviews.llvm.org/D93665
2021-01-05 20:05:31 +00:00
Atmn Patel
bf30fa7425 [LoopDeletion] Allows deletion of possibly infinite side-effect free loops
From C11 and C++11 onwards, a forward-progress requirement has been
introduced for both languages. In the case of C, loops with non-constant
conditionals that do not have any observable side-effects (as defined by
6.8.5p6) can be assumed by the implementation to terminate, and in the
case of C++, this assumption extends to all functions. The clang
frontend will emit the `mustprogress` function attribute for C++
functions (D86233, D85393, D86841) and emit the loop metadata
`llvm.loop.mustprogress` for every loop in C11 or later that has a
non-constant conditional.

This patch modifies LoopDeletion so that only loops with
the `llvm.loop.mustprogress` metadata or loops contained in functions
that are required to make progress (`mustprogress` or `willreturn`) are
checked for observable side-effects. If these loops do not have an
observable side-effect, then we delete them.

Loops without observable side-effects that do not satisfy the above
conditions will not be deleted.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D86844
2021-01-05 09:56:16 -05:00
Craig Topper
a289086bc4 [RISCV] Move shift ComplexPatterns and custom isel to PatFrags with predicates
ComplexPatterns are kind of weird, they don't call any of the predicates on their operands. And their "complexity" used for tablegen ordering purposes in the matcher table is hand specified.

This started as an attempt to just use sext_inreg + SLOIPat to implement SLOIW just to have one less Select function. The matching for the or+shl is the same as long as you know the immediate is less than 32 for SLOIW. But that didn't work out because using uimm5 with SLOIPat didn't do anything if it was a ComplexPattern.

I realized I could just use a PatFrag with the opcodes I wanted to match and an immediate predicate would then evaluate correctly. This also computes the complexity just like any other pattern does. Then I just needed to check the constraints on the immediates in the predicate. Conveniently the predicate is evaluated after the fragment has been matched. So the structure has already been checked, we just need to find the constants.

I'll note that this is unusual, I didn't find any other targets looking through operands in PatFrag predicate. There is a PredicateCodeUsesOperands feature that can be used to collect the operands into an array that is used by AMDGPU/VOP3Instructions.td. I believe that feature exists to handle commuted matching, but since the nodes here use constants, they aren't ever commuted

Differential Revision: https://reviews.llvm.org/D91901
2021-01-05 11:37:48 -08:00