1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-23 03:02:36 +01:00
Commit Graph

218769 Commits

Author SHA1 Message Date
Nikita Popov
ffc0273ec4 [IRBuilder] Deprecate CreateConstGEP1_64() without element type
This API is incompatible with opaque pointers and deprecated in
favor of the version that accepts an explicit element type.
2021-07-17 16:43:42 +02:00
Nikita Popov
2e74b1c954 [OpaquePtr] Remove uses of CreateConstGEP1_64() without element type
Remove uses of to-be-deprecated API.
2021-07-17 16:43:20 +02:00
Nikita Popov
923a0b4995 [IRBuilder] Deprecate CreateConstInBoundsGEP2_64() without element type
This API is incompatible with opaque pointers and deprecated in
favor of the version that accepts an explicit element type.
2021-07-17 16:42:39 +02:00
Nikita Popov
0911b5db54 [IRBuilder] Deprecate CreateConstGEP2_64() without element type
This API is incompatible with opaque pointers and deprecated in
favor of the version that accepts an explicit element type.
2021-07-17 16:41:51 +02:00
Kazu Hirata
a471532d2a [Analaysis, CodeGen] Remove getHotSucc (NFC)
These functions seem to be unused for at least 5 years.
2021-07-17 07:31:36 -07:00
Nikita Popov
afb69b12ce [IR] Don't accept null type in ConstantExpr::getGetElementPtr()
This is the same change as D105653, but for the constant expression
version of the API.
2021-07-17 15:59:31 +02:00
Nikita Popov
dd3e030cca [BPF] Use elementtype attribute for preserve.array/struct.index intrinsics
Use the elementtype attribute introduced in D105407 for the
llvm.preserve.array/struct.index intrinsics. It carries the
element type of the GEP these intrinsics effectively encode.

This patch:

 * Adds a verifier check that the attribute is required.
 * Adds it in the IRBuilder methods for these intrinsics.
 * Autoupgrades old bitcode without the attribute.
 * Updates the lowering code to use the attribute rather than
   the pointer element type.
 * Updates lots of tests to specify the attribute.
 * Adds -force-opaque-pointers to the intrinsic-array.ll test
   to demonstrate they work now.

https://reviews.llvm.org/D106184
2021-07-17 11:09:18 +02:00
Craig Topper
b2f709390a [RISCV] Manually emit the best shift for VSCALE lowering to improve codegen.
We assume VLENB is a multiple of 8 and previously relied on shift
pairs being optimized to an AND+SHL/SHR and computeKnownBits
removing the AND. This doesn't happen if (vlenb >> 3) gets CSEd
to have multiple uses. This patch manually emits the best shift
to workaround this.
2021-07-17 00:52:07 -07:00
Lang Hames
7bb42fce5b [ORC] Fix typo in declaration 2021-07-17 16:10:15 +10:00
jacquesguan
fa273ae7c0 [RISCV] Make VLEN no greater than 65536
Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D106134
2021-07-17 12:47:46 +08:00
Lang Hames
81a5e12cd4 [ORC] Remove LLVM-side MachO Platform runtime support.
Support for this functionality is moving to the ORC runtime.
2021-07-17 14:25:31 +10:00
Carl Ritson
9ee7bab63e [AMDGPU] Tidy SReg/SGPR definitions using template class
Use a multiclass to consistently define SReg/SGPR/TTMP register classes.
Add missing TTMP registers for 96b, 160b, 192b, 224b.

Reviewed By: foad

Differential Revision: https://reviews.llvm.org/D105800
2021-07-17 11:26:46 +09:00
Kazu Hirata
54c34b405b [Analysis] Remove isJoinDivergent (NFC)
The last use was removed on Sep 30, 2020 in commit
05ae04c396519cca9ef50d3b9cafb0cd9c87d1d7.
2021-07-16 18:23:17 -07:00
Wenlei He
51dcfc6119 [CSSPGO] Turn on iterative-BFI for CSSPGO
Iterative-BFI produces better count quality and performance when evaluated on internal benchmarks. Turning it on by default now for CSSPGO. We can consider turn it on by default for AutoFDO as well in the future.

Differential Revision: https://reviews.llvm.org/D106202
2021-07-16 17:35:49 -07:00
Matt Arsenault
acc2bc5604 Mips/GlobalISel: Remove leftover dead code 2021-07-16 20:20:55 -04:00
Matt Arsenault
c82a5efc23 AMDGPU/GlobalISel: Add a few tests for struct arguments
Test structs with pointers and vectors of pointers since this stresses
a future patch.
2021-07-16 20:20:55 -04:00
Matt Arsenault
ddf5067ad7 AMDGPU/GlobalISel: Fix some incorrect memory types in tests 2021-07-16 20:20:55 -04:00
Eli Friedman
05a71b0a6d [ScalarEvolution] Fix overflow in computeBECount.
The current implementation of computeBECount doesn't account for the
possibility that adding "Stride - 1" to Delta might overflow. For almost
all loops, it doesn't, but it's not actually proven anywhere.

To deal with this, use a variety of tricks to try to prove that the
addition doesn't overflow.  If the proof is impossible, use an alternate
sequence which never overflows.

Differential Revision: https://reviews.llvm.org/D105216
2021-07-16 16:15:18 -07:00
Joel E. Denny
3fdd4ff2ee [lit] Add --xfail-not/LIT_XFAIL_NOT
For example, I need this lately in my CI config:

LIT_XFAIL_NOT='libomptarget :: nvptx64-nvidia-cuda :: unified_shared_memory/api.c'

That test specifies an XFAIL directive, but I get an XPASS result.

Reviewed By: jhenderson

Differential Revision: https://reviews.llvm.org/D106022
2021-07-16 19:13:34 -04:00
Mehdi Amini
736e0957dc Revert "Build libSupport with -Werror=global-constructors (NFC)"
This reverts commit 1f71bcabb77df482cc0dc7bab90a73e15f3e347b.

Some platform have global destructors for std::mutex that still
needs to be fixed.
2021-07-16 22:47:04 +00:00
Mehdi Amini
e0b66fa459 Build libSupport with -Werror=global-constructors (NFC)
Ensure that libSupport does not carry any static global initializer.
libSupport can be embedded in use cases where we don't want to load all
cl::opt unless we want to parse the command line.
ManagedStatic can be used to enable lazy-initialization of globals.
2021-07-16 22:25:03 +00:00
David Green
37fc7e01a1 [ARM] Fix for matching reductions that are both sext and zext.
Fix a silly mistake that was not making sure that _both_ operands were
the correct extend code.
2021-07-16 23:11:42 +01:00
Sami Tolvanen
36181914fb Revert "ThinLTO: Fix inline assembly references to static functions with CFI"
This reverts commit 8e3b5cb39eef462943ed7556469604ce25c07a1d.

Reverting to investigate test failures.
2021-07-16 14:47:33 -07:00
Sami Tolvanen
8f7be7105b ThinLTO: Fix inline assembly references to static functions with CFI
Create an internal alias with the original name for static functions
that are renamed in promoteInternals to avoid breaking inline
assembly references to them. This version uses module inline assembly
to avoid issues with LowerTypeTestsModule.

Link: https://github.com/ClangBuiltLinux/linux/issues/1354

Reviewed By: nickdesaulniers, pcc

Differential Revision: https://reviews.llvm.org/D104058
2021-07-16 14:33:34 -07:00
Nemanja Ivanovic
b425bc6346 [PowerPC] Implement intrinsics for mtfsf[i]
This provides intrinsics for emitting instructions that set the FPSCR (`mtfsf/mtfsfi`).

The patch also conservatively marks the rounding mode as an implicit def for both since they both may set the rounding mode depending on the operands.

Reviewed By: #powerpc, qiucf

Differential Revision: https://reviews.llvm.org/D105957
2021-07-16 16:26:11 -05:00
Alexey Bataev
c5ddf465d0 [SLP]Improve calculations of the cost for reused/reordered scalars.
Part of D105020. Also, fixed FIXMEs that need to use wider vector type
when trying to calculate the cost of reused scalars. This may cause
regressions unless D100486 is landed to improve the cost estimations
for long vectors shuffling.

Differential Revision: https://reviews.llvm.org/D106060
2021-07-16 13:40:15 -07:00
LLVM GN Syncbot
f738f3fd22 [gn build] Port 0bf4b81d57b0 2021-07-16 20:32:47 +00:00
Amara Emerson
5504495d30 [GlobalISel] Fix non-pow-2 legalization of s56 stores.
s56 stores are broken down into s32 + s24 stores. During this step
both of those new stores use an anyextended s64 value, resulting in
truncating stores. With s56, the s24 requires another lower step to
make it legal, and we were crashing because we didn't expect non-pow-2
stores to also be truncating as well.

Differential Revision: https://reviews.llvm.org/D106183
2021-07-16 13:29:49 -07:00
Alexey Bataev
6af5a23481 [PATCH] D105827: [SLP]Workaround for InsertSubVector cost.
The cost of the InsertSubvector shuffle kind cost is not complete and
may end up with just extracts + inserts costs in many cases. Added
a workaround to represent it as a generic PermuteSingleSrc, which is
still pessimistic but better than InsertSubvector.

Differential Revision: https://reviews.llvm.org/D105827
2021-07-16 12:59:08 -07:00
Nico Weber
1fea8de18b [gn build] (semi-manually) port 6a4054ef060b 2021-07-16 15:54:13 -04:00
Jon Roelofs
1b0137f82a [RISCV] Compose vector subregs hierarchically
This fixes the test I broke in: https://reviews.llvm.org/D105953#2883579

Differential revision: https://reviews.llvm.org/D106168
2021-07-16 12:32:13 -07:00
Fangrui Song
25daa6d670 [llvm-readelf/llvm-readobj] Remove one-dash long options
llvm-readelf is a user-facing tool which emulates GNU readelf. Remove one-dash
long options which are not recognized by GNU style `getopt_long`. This ensures
long options cannot collide with grouped short options.

Note: the documentation (D63719)/help messages have recommended the double-dash
forms since LLVM 9.0.0.
llvm-readobj is intended as an internal tool which has some flexibility.
llvm-readelf/llvm-readobj use the same option parsing code and llvm-readobj's
one-dash long options aren't used after test migration.

Differential Revision: https://reviews.llvm.org/D106037
2021-07-16 12:03:08 -07:00
David Green
063dea2af2 [ARM] Extra MLA vecreduce tests. NFC 2021-07-16 20:01:52 +01:00
Simon Pilgrim
6a5b1b579f [X86][SSE] combineX86ShufflesRecursively - bail if constant folding fails due to oneuse limits.
Fixes issue reported on D105827 where a single shuffle of a constant (with multiple uses) was caught in an infinite loop where one shuffle (UNPCKL) used an undef arg but then that got recombined to SHUFPS as the constant value had its own undef that confused matching.....
2021-07-16 19:21:46 +01:00
Lei Huang
a6ca36648b [PowerPC] Implement XL compact math builtins
Implement a subset of builtins required for compatiblilty with AIX XL compiler.

Reviewed By: nemanjai

Differential Revision: https://reviews.llvm.org/D105930
2021-07-16 13:21:13 -05:00
Joseph Huber
f405aaa753 [OpenMP][NFC] Update the comment header for optimizations. 2021-07-16 14:13:13 -04:00
Joseph Huber
c2bfd1f7ef [OpenMP] Add IDs to OpenMP remarks
This patch adds unique idenfitiers to the existing OpenMP remarks. This makes
it easier to identify the corresponding documentation for each remark that will
be hosted in the OpenMP webpage.

Depends on D105898

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D105939
2021-07-16 14:07:03 -04:00
Joseph Huber
c740546f66 [OpenMP] Rework OpenMP remarks
This patch rewrites and reworks a few of the existing remarks to make the mmore
concise and consistent prior to writing the documentation for them.

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D105898
2021-07-16 14:07:00 -04:00
Philip Reames
e01009f13f [tests] Precommit test for D104140 2021-07-16 10:57:59 -07:00
Craig Topper
06be6a2007 [RISCV] Rename the fixed vector vwmacc tests to have the 'm' in their filenames. NFC 2021-07-16 10:43:17 -07:00
Craig Topper
ed610623c2 [RISCV] Use tail agnostic policy for fixed vector vwmacc(u).
This adds new pseudoinstructions with ForceTailAgnostic set. This
matches what we did for non-widening VMACC. We should move to a
tail policy operand on the pseudos when we expand the intrinsic
interface to include the tail policy.
2021-07-16 10:41:09 -07:00
Craig Topper
290e015b4f [RISCV] Refactor where in the multiclass hierarchy we add commutable VFMADD/VFMACC instructions. NFC
I'm preparing to add tail agnostic versions of VWMACC and VFWMACC
so this will make them more consistent.
2021-07-16 10:41:09 -07:00
Fangrui Song
a174f79c66 [docs] Update llvm-readelf supported options after D105532 2021-07-16 10:40:30 -07:00
Philip Reames
1c5ed99606 [test] Extend negative stride backedge tests to cover signed comparisons 2021-07-16 10:29:22 -07:00
Guozhi Wei
7d6ba24baf [X86FixupLEAs] Try again to transform the sequence LEA/SUB to SUB/SUB
This patch transforms the sequence
    lea (reg1, reg2), reg3
    sub reg3, reg4
to two sub instructions
    sub reg1, reg4
    sub reg2, reg4

Similar optimization can also be applied to LEA/ADD sequence.

The modifications to TwoAddressInstructionPass is to ensure the operands of ADD
instruction has expected order (the dest register of LEA should be src register
of ADD).

Differential Revision: https://reviews.llvm.org/D104684
2021-07-16 10:16:03 -07:00
Philip Reames
055a12795f [SCEV] Add tests for known negative strides in trip count logic 2021-07-16 10:08:31 -07:00
Jon Roelofs
04c73eae43 Revert "[MachineVerifier] Diagnose invalid INSERT_SUBREGs"
This reverts commit dd57ba1a17b93dbe211d04cb2d4de5f6dc898d60.

It broke some tests: http://45.33.8.238/linux/51314/step_12.txt
2021-07-16 09:53:55 -07:00
Simon Pilgrim
4e9ef1e02b [X86] Regenerate twoaddr-lea.ll test checks. 2021-07-16 17:43:36 +01:00
Simon Pilgrim
e00330583b [DAG] SelectionDAG::MaskedElementsAreZero - assert we're calling with a vector. NFCI.
Add an assertion that we've calling MaskedElementsAreZero with a vector op and that the DemandedElts arg is a matching width.

Makes the error a lot easier to grok when something else accidentally gets used.
2021-07-16 17:43:35 +01:00
Jon Roelofs
ac7796917a [MachineVerifier] Diagnose invalid INSERT_SUBREGs
Differential revision: https://reviews.llvm.org/D105953
2021-07-16 09:43:12 -07:00