Bill Wendling
0b5b31a0be
Make "movdq2q" and "movq2dq" dependent upon having SSE2 because they use the
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SSE2 registers as well as the MMX registers.
llvm-svn: 55436
2008-08-27 21:32:04 +00:00
Bill Wendling
7f52506926
Nevermind. This broke the bootstrap (?!).
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llvm-svn: 55318
2008-08-25 18:32:39 +00:00
Bill Wendling
f86b246fdb
MOVQ2DQ and MOVQ2DQ use SSE2. We should conditionalize the use of these
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instructions on having SSE2.
llvm-svn: 55317
2008-08-25 18:20:52 +00:00
Anton Korobeynikov
be3a5a5ce9
Provide a 64 bit variant of mmx.maskmovq intrinsic lowering.
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Is there way to avoid explicit target check?
llvm-svn: 55238
2008-08-23 15:53:19 +00:00
Dan Gohman
e409b06d46
Fix comment spacing.
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llvm-svn: 55047
2008-08-20 13:46:21 +00:00
Nate Begeman
af01bfff99
SSE codegen for vsetcc nodes
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llvm-svn: 53719
2008-07-17 16:51:19 +00:00
Evan Cheng
fc6645a382
Fix a number of encoding bugs. SSE 4.1 instructions MPSADBWrri, PINSRDrr, etc. have 8-bits immediate field (ImmT == Imm8).
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llvm-svn: 48360
2008-03-14 07:39:27 +00:00
Andrew Lenharth
ad29a49169
Add lock prefix support to x86. Also add the instructions necessary for the atomic ops. They are still marked pseudo, since I cannot figure out what format to use, but they are the correct opcode.
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llvm-svn: 47795
2008-03-01 13:37:02 +00:00
Nate Begeman
810b85bde8
SSE4.1 64b integer insert/extract pattern support
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Move formats into the formats file
llvm-svn: 47035
2008-02-12 22:51:28 +00:00
Chris Lattner
ad9a6ccb83
Remove attribution from file headers, per discussion on llvmdev.
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llvm-svn: 45418
2007-12-29 20:36:04 +00:00
Evan Cheng
eba18a1952
Fix JIT encoding for CMPSD as well.
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llvm-svn: 45268
2007-12-20 19:57:09 +00:00
Chris Lattner
c6fd78dec1
Fix the JIT encoding of cmp*ss, which aborts with this assertion currently:
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X86CodeEmitter.cpp:378: failed assertion `0 && "Immediate size not set!"'
I *think* this is right, but Evan, please verify. It also looks like
CMPSDrr and maybe others are missing this info. Evan, plz investigate.
llvm-svn: 45074
2007-12-16 20:12:41 +00:00
Evan Cheng
3493ec0ce1
Redo and generalize previously removed opt for pinsrw: (vextract (v4i32 bc (v4f32 s2v (f32 load ))), 0) -> (i32 load )
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llvm-svn: 40628
2007-07-31 08:04:03 +00:00
