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51 Commits

Author SHA1 Message Date
Daniel Sanders
6ffe6fc99c [mips][msa] Added support for matching mod_[us] from normal IR (i.e. not intrinsics) 
llvm-svn: 191737
 2013-10-01 10:22:35 +00:00
Daniel Sanders
0987676281 [mips][msa] Implemented insert.d intrinsic. 
This intrinsic is lowered into an equivalent INSERT_VECTOR_ELT which is
further lowered into a sequence of insert.w's on MIPS32.

llvm-svn: 191521
 2013-09-27 13:36:54 +00:00
Daniel Sanders
3c43957555 [mips][msa] Implemented fill.d intrinsic. 
This intrinsic is lowered into an equivalent BUILD_VECTOR which is further
lowered into a sequence of insert.w's on MIPS32.

llvm-svn: 191519
 2013-09-27 13:20:41 +00:00
Daniel Sanders
935673af60 [mips][msa] Implemented copy_[us].d intrinsic. 
This intrinsic is lowered into equivalent copy_s.w instructions during
legalization.

llvm-svn: 191518
 2013-09-27 13:04:21 +00:00
Daniel Sanders
8c83ddcdd2 [mips][msa] Implemented insert_vector_elt for v4f32 and v2f64. 
For v4f32 and v2f64, INSERT_VECTOR_ELT is matched by a pseudo-insn which is
later expanded to appropriate insve.[wd] insns.

llvm-svn: 191515
 2013-09-27 12:31:32 +00:00
Daniel Sanders
0bb1b5a37f [mips][msa] Implemented extract_vector_elt for v4f32 or v2f64 
For v4f32 and v2f64, EXTRACT_VECTOR_ELT is matched by a pseudo-insn which may
be expanded to subregister copies and/or instructions as appropriate.

llvm-svn: 191514
 2013-09-27 12:17:32 +00:00
Daniel Sanders
0f009e6be5 [mips][msa] Added support for MSA registers to copyPhysReg 
llvm-svn: 191512
 2013-09-27 12:03:51 +00:00
Daniel Sanders
8e7e5fd076 [mips][msa] Added support for matching splati from normal IR (i.e. not intrinsics) 
Updated some of the vshf since they (correctly) emit splati's now

llvm-svn: 191511
 2013-09-27 11:48:57 +00:00
Daniel Sanders
d13fea547a [mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode. 
llvm-svn: 191498
 2013-09-27 10:08:31 +00:00
Daniel Sanders
6a20248b3a [mips][msa] Expand all truncstores and loadexts for MSA as well as DSP 
llvm-svn: 191496
 2013-09-27 09:44:59 +00:00
Daniel Sanders
27836999cd [mips][msa] Added missing check in performSRACombine 
Reviewers: jacksprat, dsanders

Reviewed By: dsanders

Differential Revision: http://llvm-reviews.chandlerc.com/D1755

llvm-svn: 191495
 2013-09-27 09:25:29 +00:00
Daniel Sanders
d110591231 [mips][msa] Added support for matching pckev, and pckod from normal IR (i.e. not intrinsics) 
llvm-svn: 191306
 2013-09-24 14:53:25 +00:00
Daniel Sanders
48059bf5ef [mips][msa] Added support for matching ilv[lr], ilvod, and ilvev from normal IR (i.e. not intrinsics) 
llvm-svn: 191304
 2013-09-24 14:36:12 +00:00
Daniel Sanders
db41b542e8 [mips][msa] Added support for matching shf from normal IR (i.e. not intrinsics) 
llvm-svn: 191302
 2013-09-24 14:20:00 +00:00
Daniel Sanders
7c64721346 [mips][msa] Added support for matching vshf from normal IR (i.e. not intrinsics) 
llvm-svn: 191301
 2013-09-24 14:02:15 +00:00
Daniel Sanders
e154d03143 [mips][msa] Remove the VSPLAT and VSPLATD nodes in favour of matching BUILD_VECTOR. 
Most constant BUILD_VECTOR's are matched using ComplexPatterns which cover
bitcasted as well as normal vectors. However, it doesn't seem to be possible to
match ldi.[bhwd] in a type-agnostic manner (e.g. to support the widest range of
immediates, it should be possible to use ldi.b to load v2i64) using TableGen so
ldi.[bhwd] is matched using custom code in MipsSEISelDAGToDAG.cpp

This made the majority of the constant splat BUILD_VECTOR lowering redundant.
The only transformation remaining for constant splats is when an (up-to) 32-bit
constant splat is possible but the value does not fit into a 10-bit signed
integer. In this case, the BUILD_VECTOR is transformed into a bitcasted
BUILD_VECTOR so that fill.[bhw] can be used to splat the vector from a GPR32
register (which is initialized using the usual lui/addui sequence).

There are no additional tests since this is a re-implementation of previous
functionality. The change is intended to make it easier to implement some of
the upcoming instruction selection patches since they can rely on existing
support for BUILD_VECTOR's in the DAGCombiner.

compare_float.ll changed slightly because a BITCAST is no longer
introduced during legalization.

llvm-svn: 191299
 2013-09-24 13:33:07 +00:00
Daniel Sanders
1c08f8b17d [mips][msa] Non-constant BUILD_VECTOR's should be expanded to INSERT_VECTOR_ELT instead of memory operations. 
The resulting code is the same length, but doesnt cause memory traffic or latency.

llvm-svn: 191297
 2013-09-24 13:16:15 +00:00
Daniel Sanders
d201758a30 [mips][msa] Added partial support for matching fmax_a from normal IR (i.e. not intrinsics) 
This covers the case where fmax_a can be used to implement ISD::FABS.

llvm-svn: 191296
 2013-09-24 13:02:08 +00:00
Daniel Sanders
fe71effbbd [mips][msa] Added support for matching andi, ori, nori, and xori from normal IR (i.e. not intrinsics) 
llvm-svn: 191293
 2013-09-24 12:32:47 +00:00
Daniel Sanders
f05ed8bd9a [mips][msa] Added support for matching max, maxi, min, mini from normal IR (i.e. not intrinsics) 
llvm-svn: 191291
 2013-09-24 12:18:31 +00:00
Daniel Sanders
0167ec55f4 [mips][msa] Added support for matching bsel and bseli from normal IR (i.e. not intrinsics) 
This required correcting the definition of the bsel and bseli intrinsics.

llvm-svn: 191290
 2013-09-24 12:04:44 +00:00
Daniel Sanders
9a3de1f604 [mips][msa] Added support for matching comparisons from normal IR (i.e. not intrinsics) 
MIPS SelectionDAG changes:
* Added VCEQ, VCL[ET]_[SU] nodes to represent vector comparisons that produce a bitmask.

llvm-svn: 191286
 2013-09-24 10:46:19 +00:00
Daniel Sanders
362149b5a7 [mips][msa] Added support for matching slli, srai, and srli from normal IR (i.e. not intrinsics) 
llvm-svn: 191285
 2013-09-24 10:28:18 +00:00
Daniel Sanders
ced4e4005c [mips][msa] Added support for matching addvi, and subvi from normal IR (i.e. not intrinsics) 
llvm-svn: 191203
 2013-09-23 14:29:55 +00:00
Daniel Sanders
34cb8f3e4d [mips][msa] Added support for matching insert and copy from normal IR (i.e. not intrinsics) 
Changes to MIPS SelectionDAG:
* Added nodes VEXTRACT_[SZ]EXT_ELT to represent extract and extend in a single
  operation and implemented the DAG combines necessary to fold sign/zero
  extends into the extract.

llvm-svn: 191199
 2013-09-23 14:03:12 +00:00
Daniel Sanders
d1df1263eb [mips][msa] Added support for matching pcnt from normal IR (i.e. not intrinsics) 
llvm-svn: 191198
 2013-09-23 13:40:21 +00:00
Daniel Sanders
7d945d142d [mips][msa] Added support for matching nor from normal IR (i.e. not intrinsics) 
llvm-svn: 191195
 2013-09-23 13:22:24 +00:00
Daniel Sanders
91c78d1d33 [mips][msa] Added support for matching and, or, and xor from normal IR (i.e. not intrinsics) 
llvm-svn: 191194
 2013-09-23 12:57:42 +00:00
Daniel Sanders
d3c403c386 [mips][msa] Implemented build_vector using ldi, fill, and custom SelectionDAG nodes (VSPLAT and VSPLATD) 
Note: There's a later patch on my branch that re-implements this to select
build_vector without the custom SelectionDAG nodes. The future patch avoids
the constant-folding problems stemming from the custom node (i.e. it doesn't
need to re-implement all the DAG combines related to BUILD_VECTOR).

Changes to MIPS specific SelectionDAG nodes:
* Added VSPLAT
    This is a special case of BUILD_VECTOR that covers the case the
    BUILD_VECTOR is a splat operation.
* Added VSPLATD
    This is a special case of VSPLAT that handles the cases when v2i64 is legal

llvm-svn: 191191
 2013-09-23 12:02:46 +00:00
Daniel Sanders
16a6e0ac3d [mips][msa] Added test cases that were supposed to be part of r190507, r190509, r190512, and r190518. 
llvm-svn: 190522
 2013-09-11 12:39:25 +00:00
Daniel Sanders
e3f2e5de18 [mips][msa] Added support for matching mulv, nlzc, sll, sra, srl, and subv from normal IR (i.e. not intrinsics) 
llvm-svn: 190518
 2013-09-11 11:58:30 +00:00
Daniel Sanders
96466ff8b4 [mips][msa] Added support for matching fadd, fdiv, flog2, fmul, frint, fsqrt, and fsub from normal IR (i.e. not intrinsics) 
llvm-svn: 190512
 2013-09-11 10:51:30 +00:00
Daniel Sanders
a52c7f09dc [mips][msa] Added support for matching div_[su] from normal IR (i.e. not intrinsics) 
llvm-svn: 190509
 2013-09-11 10:38:58 +00:00
Daniel Sanders
f68b00e629 [mips][msa] Added support for matching addv from normal IR (i.e. not intrinsics) 
The corresponding intrinsic is now lowered into equivalent IR (ISD::ADD) before instruction selection.

llvm-svn: 190507
 2013-09-11 10:28:16 +00:00
Daniel Sanders
534d28aa11 [mips][msa] Corrected the definition of the dotp_[su].[hwd] intrinsics 
The elements of the operands should be half the width of the elements of
the result.

llvm-svn: 190505
 2013-09-11 09:59:17 +00:00
Daniel Sanders
32227b7995 [mips][msa] Removed unsupported dot product instructions (dotp_[su].b) 
The dotp_[su].b instructions never existed in any revision of the MSA spec.

llvm-svn: 190398
 2013-09-10 09:51:43 +00:00
Daniel Sanders
7d6b0c31fc [mips][msa] Added bnz.df, bnz.v, bz.df, and bz.v 
These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes,
are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as
a branch/mov sequence to evaluate to 0 or 1.

Note: The resulting code is sub-optimal since it doesnt seem to be possible
to feed the result of an intrinsic directly into a brcond. At the moment
it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily
evaluates the boolean twice.

llvm-svn: 189478
 2013-08-28 12:14:50 +00:00
Daniel Sanders
86a3b104b1 [mips][msa] Added load/store intrinsics. 
llvm-svn: 189476
 2013-08-28 12:04:29 +00:00
Daniel Sanders
6583601738 [mips][msa] Added move.v 
llvm-svn: 189471
 2013-08-28 10:44:47 +00:00
Daniel Sanders
21800e80c1 [mips][msa] Added cfcmsa, and ctcmsa 
The MSA control registers have been added as reserved registers,
and are only used via ISD::Copy(To|From)Reg. The intrinsics are lowered
into these nodes.

llvm-svn: 189468
 2013-08-28 10:26:24 +00:00
Daniel Sanders
3740f20366 [mips][msa] Added f[cs]af, f[cs]or, f[cs]ueq, f[cs]ul[et], f[cs]une, fsun, ftrunc_[su], hadd_[su], hsub_[su], sr[al]r, sr[al]ri 
llvm-svn: 189467
 2013-08-28 10:12:09 +00:00
Daniel Sanders
6d33546b4a [mips][msa] Summarize tests 
Adds a comment to the start of each test summarizing the area the test covers.

llvm-svn: 189465
 2013-08-28 10:02:29 +00:00
Daniel Sanders
87ee4173d5 [mips][msa] Added tests for and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v when non-byte vectors are used. 
Note that all of these tests use ld.b and st.b for the loads and stores
regardless of the data size. This is because the definition of bitcast is
equivalent to a store/load sequence and DAG combiner accordingly folds bitcasts
to/from v16i8 into the load/store nodes to product load/store nodes with
type v16i8.

llvm-svn: 189333
 2013-08-27 10:16:17 +00:00
Daniel Sanders
00e8a9cb19 [mips][msa] Added spill/reload support 
llvm-svn: 189332
 2013-08-27 10:04:21 +00:00
Daniel Sanders
b2c1c16a0a [mips][msa] Added bitconverts for vector types for big and little-endian 
llvm-svn: 189330
 2013-08-27 09:40:30 +00:00
Daniel Sanders
30561c36b8 [mips][msa] Removed fcge, fcgt, fsge, fsgt 
These instructions were present in a draft spec but were removed before
publication.

llvm-svn: 188782
 2013-08-20 09:41:47 +00:00
Daniel Sanders
91c40d80de [mips][msa] Added insve 
llvm-svn: 188777
 2013-08-20 09:22:54 +00:00
Daniel Sanders
15341e9a12 [mips][msa] Added and.v, bmnz.v, bmz.v, bsel.v, nor.v, or.v, xor.v 
llvm-svn: 188767
 2013-08-20 08:38:21 +00:00
Jack Carter
2c2f78cead [Mips][msa] Added the simple builtins (madd_q to xori) 
Includes:
madd_q, maddr_q, maddv, max_[asu], maxi_[su], min_[asu], mini_[su], mod_[su],
msub_q, msubr_q, msubv, mul_q, mulr_q, mulv, nloc, nlzc, nori, ori, pckev,
pckod, pcnt, sat_[su], shf, sld, sldi, sll, slli, splat, splati, sr[al],
sr[al]i, subs_[su], subss_u, subus_s, subv, subvi, vshf, xori

Patch by Daniel Sanders

llvm-svn: 188460
 2013-08-15 14:22:07 +00:00
Jack Carter
8798c3bae2 [Mips][msa] Added the simple builtins (fadd to ftq) 
Includes:
fadd, fceq, fcg[et], fclass, fcl[et], fcne, fcun, fdiv, fexdo, fexp2,
fexup[lr], ffint_[su], ffql, ffqr, fill, flog2, fmadd, fmax, fmax_a, fmin,
fmin_a, fmsub, fmul, frint, frcp, frsqrt, fseq, fsge, fsgt, fsle, fslt,
fsne, fsqr, fsub, ftint_s, ftq

Patch by Daniel Sanders

llvm-svn: 188458
 2013-08-15 13:45:36 +00:00