2 Commits

Author	SHA1	Message	Date
Daniel Sanders	d13fea547a	[mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode. ... llvm-svn: 191498	2013-09-27 10:08:31 +00:00
Daniel Sanders	7d6b0c31fc	[mips][msa] Added bnz.df, bnz.v, bz.df, and bz.v ... These intrinsics are legalized to V(ALL|ANY)_(NON)?ZERO nodes, are matched as SN?Z_[BHWDV]_PSEUDO pseudo's, and emitted as a branch/mov sequence to evaluate to 0 or 1. Note: The resulting code is sub-optimal since it doesnt seem to be possible to feed the result of an intrinsic directly into a brcond. At the moment it uses (SETCC (VALL_ZERO $ws), 0, SETEQ) and similar which unnecessarily evaluates the boolean twice. llvm-svn: 189478	2013-08-28 12:14:50 +00:00