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7196 Commits

Author SHA1 Message Date
Dale Johannesen
469ed8e17e Skeleton of post-RA scheduler; doesn't do anything yet. 
Change name of -sched option and DEBUG_TYPE to
pre-RA-sched; adjust testcases.

llvm-svn: 39816
 2007-07-13 17:13:54 +00:00
Chris Lattner
7cba3578aa Fix CodeGen/Generic/print-arith-fp.ll on sparc (PR1551) 
llvm-svn: 39813
 2007-07-13 16:24:10 +00:00
Dale Johannesen
eb2c2823e3 ARM: make branch folder remove unconditional branches 
following jump tables that it earlier inserted.  This
would be OK on other targets but is needed for correctness
only on ARM (constant islands needs to find jump tables).

llvm-svn: 39782
 2007-07-12 16:45:35 +00:00
Chris Lattner
7eea439048 another missed SSE optimization 
llvm-svn: 39772
 2007-07-12 06:31:38 +00:00
Bruno Cardoso Lopes
27f5beafb2 Added support for Mips specific GAS directives 
Fixed print immediate 
Fixed Identation on MipsISelDAGToDAG.cpp

llvm-svn: 39764
 2007-07-11 23:24:41 +00:00
Bruno Cardoso Lopes
e21704313d Added support for framepointer 
Prologue/Epilogue support fp,ra save/restore and use the stack frame the right
way!

llvm-svn: 39763
 2007-07-11 23:21:31 +00:00
Bruno Cardoso Lopes
0ba66ea1dc Now that stack is represented the right way, LOA starts at 0 
llvm-svn: 39761
 2007-07-11 23:17:41 +00:00
Bruno Cardoso Lopes
be14b3c16c Fixed AddLiveOut issues 
FI's created the write way to represent Mips stack

llvm-svn: 39760
 2007-07-11 23:16:16 +00:00
Bruno Cardoso Lopes
bc1b534410 Removed unused immediate PatLeaf, fixed lui instruction 
llvm-svn: 39759
 2007-07-11 22:47:02 +00:00
Bruno Cardoso Lopes
a851ed6989 Added MipsMachineFunction class, to hold Mips dinamic stack info when inserting Prologue/Epilog 
llvm-svn: 39758
 2007-07-11 22:44:21 +00:00
Lauro Ramos Venancio
0ad4cde600 Handle packed structs in the CBackend. 
llvm-svn: 39752
 2007-07-11 19:56:53 +00:00
Dale Johannesen
cacc6dbeb6 Fix hang compiling TimberWolf (allow for islands 
of size other than 4).

llvm-svn: 39743
 2007-07-11 18:32:38 +00:00
Lauro Ramos Venancio
18fc770fd0 Assert when TLS is not implemented. 
llvm-svn: 39737
 2007-07-11 17:19:51 +00:00
Chris Lattner
ef484ab964 Fix an oversight: for modules with no other identifying target info, 
the sparc backend should be preferred when running on sparcs.

llvm-svn: 39142
 2007-07-11 16:32:10 +00:00
Evan Cheng
f6d010e93d Didn't mean the last commit. Revert. 
llvm-svn: 38515
 2007-07-10 22:00:16 +00:00
Dale Johannesen
ecef839eaa Fix fp_constant_op failure. 
llvm-svn: 38514
 2007-07-10 21:53:30 +00:00
Evan Cheng
05c784cc30 Update. 
llvm-svn: 38513
 2007-07-10 21:49:47 +00:00
Dale Johannesen
7325a82196 fix 80 columnn violations, increasing the world's 
pedantic satisfaction level.

llvm-svn: 38512
 2007-07-10 20:53:41 +00:00
Chris Lattner
abcdeef610 add a note 
llvm-svn: 38507
 2007-07-10 20:03:50 +00:00
Evan Cheng
abcf3842bb Remove clobbersPred. Add an OptionalDefOperand to instructions which have the 's' bit. 
llvm-svn: 38501
 2007-07-10 18:08:01 +00:00
Evan Cheng
0ab209fa54 Remove clobbersPred. 
llvm-svn: 38500
 2007-07-10 18:07:08 +00:00
Dan Gohman
928144b051 Define non-intrinsic instructions for vector min, max, sqrt, rsqrt, and rcp, 
in addition to the intrinsic forms. Add spill-folding entries for these new
instructions, and for the scalar min and max instrinsic instructions which
were missing. And add some preliminary ISelLowering code for using the new
non-intrinsic vector sqrt instruction, and fneg and fabs.

llvm-svn: 38478
 2007-07-10 00:05:58 +00:00
Dan Gohman
81cfdc2f19 Change getCopyToParts and getCopyFromParts to always use target-endian 
register ordering, for both physical and virtual registers. Update the PPC
target lowering for calls to expect registers for the call result to
already be in target order.

llvm-svn: 38471
 2007-07-09 20:59:04 +00:00
Chris Lattner
4810c53b05 The various "getModuleMatchQuality" implementations should return 
zero if they see a target triple they don't understand.

llvm-svn: 38463
 2007-07-09 17:25:29 +00:00
Evan Cheng
d9d3be078c No need for ccop anymore. 
llvm-svn: 37965
 2007-07-06 23:34:09 +00:00
Evan Cheng
92e624a6f7 Incorrect check. 
llvm-svn: 37962
 2007-07-06 23:23:19 +00:00
Evan Cheng
3b1b3eba6a Do away with ImmutablePredicateOperand. 
llvm-svn: 37961
 2007-07-06 23:22:46 +00:00
Evan Cheng
88acbacd35 isUnpredicatedTerminator should treat conditional branches as unpredicated terminator. 
llvm-svn: 37960
 2007-07-06 23:22:03 +00:00
Evan Cheng
776d4d6e11 Do away with ImmutablePredicateOperand. 
llvm-svn: 37959
 2007-07-06 23:21:02 +00:00
Rafael Espindola
7b3de98989 Add the byval attribute 
llvm-svn: 37940
 2007-07-06 10:57:03 +00:00
Evan Cheng
721b83bbe6 Print the s bit if the instruction is toggled to its CPSR setting form. 
llvm-svn: 37932
 2007-07-06 01:01:34 +00:00
Evan Cheng
c2c0b495ed PredicateDefOperand -> OptionalDefOperand. 
llvm-svn: 37931
 2007-07-06 01:00:49 +00:00
Evan Cheng
0adaea7381 Add OptionalDefOperand to stand for optionally defined result. 
llvm-svn: 37930
 2007-07-06 01:00:16 +00:00
Evan Cheng
96254545ae Initial ARM JIT support by Raul Fernandes Herbster. 
llvm-svn: 37926
 2007-07-05 21:15:40 +00:00
Anton Korobeynikov
e8215d1780 Proper flag __alloca call 
llvm-svn: 37923
 2007-07-05 20:36:08 +00:00
Evan Cheng
25450e48ca Doh 
llvm-svn: 37917
 2007-07-05 17:21:33 +00:00
Evan Cheng
04d3ebc699 Unbreak the build. 
llvm-svn: 37915
 2007-07-05 17:13:56 +00:00
Evan Cheng
a59422068f Unbreak the build. 
llvm-svn: 37914
 2007-07-05 17:13:19 +00:00
Gabor Greif
5f705671e4 Here is the bulk of the sanitizing. 
Almost all occurrences of "bytecode" in the sources have been eliminated.

llvm-svn: 37913
 2007-07-05 17:07:56 +00:00
Chris Lattner
ff6104f9d5 the arm backend is not building, temporarily disable it. 
llvm-svn: 37911
 2007-07-05 16:11:52 +00:00
Evan Cheng
be54fdf431 Reflects the chanegs made to PredicateOperand. 
llvm-svn: 37898
 2007-07-05 07:18:20 +00:00
Evan Cheng
3d2cfd8bb1 Added ARM::CPSR to represent ARM CPSR status register. 
llvm-svn: 37897
 2007-07-05 07:17:13 +00:00
Evan Cheng
2403cc41ea Unfortunately we now require C++ code to isel Bcc, conditional moves, etc. 
llvm-svn: 37896
 2007-07-05 07:15:27 +00:00
Evan Cheng
ef8a1bcbc3 Each ARM use predicate operand is now made up of two components. The new component is the CPSR register. 
llvm-svn: 37895
 2007-07-05 07:13:32 +00:00
Evan Cheng
4af116139b Added ARM::CPSR to represent ARM CPSR status register. 
llvm-svn: 37894
 2007-07-05 07:11:03 +00:00
Evan Cheng
9b7432c311 PPC conditional branch predicate does not change after isel. 
llvm-svn: 37893
 2007-07-05 07:09:50 +00:00
Evan Cheng
8b0cbaff08 - Added zero_reg def to stand for register 0. 
- Added two variants of PredicateOperand: ImmutablePredicateOperand, whose predicate does not change after isel; PredicateDefOperand, which represent a predicate defintion operand.

llvm-svn: 37892
 2007-07-05 07:09:09 +00:00
Evan Cheng
50367dfc3e Do not check isPredicated() on non-predicable instructions. 
llvm-svn: 37891
 2007-07-05 07:06:46 +00:00
Dale Johannesen
9072b65b0b Refactor X87 instructions. As a side effect, all 
their names are changed.

llvm-svn: 37876
 2007-07-04 21:07:47 +00:00
Bill Wendling
2e66551f22 Support generation of GR64 to MMX code in the JIT. 
llvm-svn: 37866
 2007-07-04 01:29:22 +00:00