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276b736496
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Author SHA1 Message Date
Duncan Sands
276b736496 Fix PR3393, which amounts to a bug in the expensive 
checking logic.  Rather than make the checking more
complicated, I've tweaked some logic to make things
conform to how the checking thought things ought to
be, since this results in a simpler "mental model".

llvm-svn: 63048
 2009-01-26 21:54:18 +00:00
Dan Gohman
4613b5e807 At Nick Lewycky's request, rename this test with a more informative name. 
llvm-svn: 63042
 2009-01-26 21:36:31 +00:00
Evan Cheng
ec03e0cd3b Enhance logic in X86DAGToDAGISel::PreprocessForRMW which move load inside callseq_start to allow it to be folded into a call. It was not considering the cases where a token factor is between the load and the callseq_start. 
llvm-svn: 63022
 2009-01-26 18:43:34 +00:00
Nate Begeman
92efc4f0ce Map address space 256 to gs; similar mappings could be supported for the 
other x86 segments.  address space 0 is stack/default, 1-255 are reserved for
client use.

llvm-svn: 62980
 2009-01-26 01:24:32 +00:00
Torok Edwin
3f54410405 revert this patch for now, because Codegen does still want to generate SSE code, 
for example in the case of va-args. XFAIL associated tests.

llvm-svn: 62972
 2009-01-25 20:21:24 +00:00
Torok Edwin
49b1d3e3cc If user explicitly asks not to use SSE, don't force it. This fixes LLVM part of PR3402. 
llvm-svn: 62967
 2009-01-25 17:58:56 +00:00
Evan Cheng
4ebe9b79fa Teach 2addr pass to be do more commuting. If both uses of a two-address instruction are killed, but the first operand has a use before and after the def, commute if the second operand does not suffer from the same issue. 
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1                                                                                                                                     
%reg1029<def> = MOV8rr %reg1028                                                                                                                                                      
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>                                                                                                                            
insert => %reg1030<def> = MOV8rr %reg1028                                                                                                                                            
%reg1030<def> = ADD8rr %reg1028<kill>, %reg1029<kill>, %EFLAGS<imp-def,dead>                                                                                                         

In this case, it might not be possible to coalesce the second MOV8rr                                                                                                                 
instruction if the first one is coalesced. So it would be profitable to                                                                                                              
commute it:                                                                                                                                                                          
%reg1028<def> = EXTRACT_SUBREG %reg1027<kill>, 1                                                                                                                                     
%reg1029<def> = MOV8rr %reg1028                                                                                                                                                      
%reg1029<def> = SHR8ri %reg1029, 7, %EFLAGS<imp-def,dead>                                                                                                                            
insert => %reg1030<def> = MOV8rr %reg1029                                                                                                                                            
%reg1030<def> = ADD8rr %reg1029<kill>, %reg1028<kill>, %EFLAGS<imp-def,dead>

llvm-svn: 62954
 2009-01-25 03:53:59 +00:00
Dan Gohman
14a8caaef9 Add a PR comment to this test. 
llvm-svn: 62921
 2009-01-24 17:32:54 +00:00
Evan Cheng
4a5296ec5f Update test to reflect command line option name change. 
llvm-svn: 62836
 2009-01-23 05:45:31 +00:00
Dan Gohman
a6e5948fce Don't create ISD::FNEG nodes after legalize if they aren't legal. 
Simplify x+0 to x in unsafe-fp-math mode. This avoids a bunch of
redundant work in many cases, because in unsafe-fp-math mode,
ISD::FADD with a constant is considered free to negate, so the
DAGCombiner often negates x+0 to -0-x thinking it's free, when
in reality the end result is -x, which is more expensive than x.

Also, combine x*0 to 0.

This fixes PR3374.

llvm-svn: 62789
 2009-01-22 21:58:43 +00:00
Devang Patel
386023e3f0 Do not use buggy llvm-gcc to generate testcases. 
llvm-svn: 62770
 2009-01-22 18:28:11 +00:00
Bill Wendling
58a51ca0f9 Now with RUN line. 
llvm-svn: 62716
 2009-01-21 21:28:03 +00:00
Bill Wendling
1eb2ec148b Run this through -simplifycfg and -mem2reg to test only what we need to test. 
llvm-svn: 62714
 2009-01-21 21:02:27 +00:00
Dan Gohman
d021a20409 Simplify ReduceLoadWidth's logic: it doesn't need several different 
special cases after producing the new reduced-width load, because the
new load already has the needed adjustments built into it. This fixes
several bugs due to the special cases, including PR3317.

llvm-svn: 62692
 2009-01-21 15:17:51 +00:00
Dan Gohman
704f0d5879 Fix a recent regression. ClrOpcode is not set for i8; for i8, if 
we want to clear %ah to zero before a division, just use a
zero-extending mov to %al. This fixes PR3366.

llvm-svn: 62691
 2009-01-21 14:50:16 +00:00
Evan Cheng
0ed6a9d7e0 Favors generating "not" over "xor -1". For example. 
unsigned test(unsigned a) {
  return ~a;
}
llvm used to generate:
movl    $4294967295, %eax
xorl    4(%esp), %eax

Now it generates:
movl      4(%esp), %eax
notl      %eax

It's 3 bytes shorter.

llvm-svn: 62661
 2009-01-21 02:09:05 +00:00
Owen Anderson
10ad717dc8 Be more aggressive about renumbering vregs after splitting them. 
llvm-svn: 62639
 2009-01-21 00:13:28 +00:00
Evan Cheng
5bea79c062 Fix PR3243: a LiveVariables bug. When HandlePhysRegKill is checking whether the last reference is also the last def (i.e. dead def), it should also check if last reference is the current machine instruction being processed. This can happen when it is processing a physical register use and setting the current machine instruction as sub-register's last ref. 
llvm-svn: 62617
 2009-01-20 21:25:12 +00:00
Evan Cheng
0151af3a61 Add test case for PR3154. 
llvm-svn: 62604
 2009-01-20 19:29:54 +00:00
Bill Wendling
68171bde8e Testcase for limited precision stuff. 
llvm-svn: 62572
 2009-01-20 06:23:59 +00:00
Dan Gohman
ff4c4ab39f Fix a dagcombine to not generate loads of non-round integer types, 
as its comment says, even in the case where it will be generating
extending loads. This fixes PR3216.

llvm-svn: 62557
 2009-01-20 01:06:45 +00:00
Evan Cheng
5ee5ba12be Make linear scan's trivial coalescer slightly more aggressive. 
llvm-svn: 62547
 2009-01-20 00:16:18 +00:00
Dale Johannesen
5508ead868 Move & restructure test per review. 
llvm-svn: 62538
 2009-01-19 22:33:12 +00:00
Dan Gohman
af4e583c93 Fix SelectionDAG::ReplaceAllUsesWith to behave correctly when 
uses are added to the From node while it is processing From's
use list, because of automatic local CSE. The fix is to avoid
visiting any new uses.

Fix a few places in the DAGCombiner that assumed that after
a RAUW call, the From node has no users and may be deleted.

This fixes PR3018.

llvm-svn: 62533
 2009-01-19 21:44:21 +00:00
Dale Johannesen
31f3cac06b compile-time fmod was done incorrectly. PR 3316. 
llvm-svn: 62528
 2009-01-19 21:17:05 +00:00
Evan Cheng
06cfade044 DIVREM isel deficiency: If sign bit is known zero, zero out DX/EDX/RDX instead of sign extending the low part (in AX/EAX/RAX) into it. 
llvm-svn: 62519
 2009-01-19 19:06:11 +00:00
Evan Cheng
53e83a2eb9 Now not UINT_TO_FP is legal (it's marked custom), dag combiner won't 
optimize it to a SINT_TO_FP when the sign bit is known zero. X86 isel should perform the optimization itself.

llvm-svn: 62504
 2009-01-19 08:08:22 +00:00
Chris Lattner
6f03811071 Fix rdar://6505632, an llc crash on 483.xalancbmk 
llvm-svn: 62470
 2009-01-18 20:35:00 +00:00
Bill Wendling
bca1d8ae5a Testcase for last commit. 
llvm-svn: 62418
 2009-01-17 07:42:44 +00:00
Evan Cheng
182d9c4c9f Fix MatchAddress bug that's preventing negative displacement from being folded in 64-bit mode. 
llvm-svn: 62413
 2009-01-17 07:09:27 +00:00
Mon P Wang
563134282c Simplify extract element of a scalar to vector. 
llvm-svn: 62383
 2009-01-17 00:07:25 +00:00
Dan Gohman
cd46de9bdc Disable the post-RA scheduler on this test, since it uses a 
simple %prcontext which doesn't find what it's looking for
if the scheduler has rearranged the instructions.

llvm-svn: 62363
 2009-01-16 21:40:12 +00:00
Evan Cheng
c4d19d6e8c CreateVirtualRegisters does trivial copy coalescing. If a node def is used by a single CopyToReg, it reuses the virtual register assigned to the CopyToReg. This won't work for SDNode that is a clone or is itself cloned. Disable this optimization for those nodes or it can end up with non-SSA machine instructions. 
llvm-svn: 62356
 2009-01-16 20:57:18 +00:00
Bill Wendling
c9e856fbfd Add support for non-zero __builtin_return_address values on X86. 
llvm-svn: 62338
 2009-01-16 19:25:27 +00:00
Mon P Wang
e235ba591f Added missing support to widen an operand from a bit convert. 
llvm-svn: 62285
 2009-01-15 22:43:38 +00:00
Mon P Wang
4cfe965df2 Expand insert/extract of a <4 x i32> with a variable index. 
llvm-svn: 62281
 2009-01-15 21:10:20 +00:00
Rafael Espindola
0aba6c9435 Add the private linkage. 
llvm-svn: 62279
 2009-01-15 20:18:42 +00:00
Dan Gohman
8c835f6285 Disable the register+memory forms of the bt instructions for now. Thanks 
to Eli for pointing out that these forms don't ignore the high bits of
their index operands, and as such are not immediately suitable for use
by isel.

llvm-svn: 62194
 2009-01-13 23:23:30 +00:00
Duncan Sands
975f2428ba When replacing uses and the same node is reached 
via two paths, process it once not twice, d'oh!
Analysis, testcase and original patch thanks to
Mon Ping Wang.

llvm-svn: 62169
 2009-01-13 15:17:14 +00:00
Evan Cheng
a706a020bc FIX llvm-gcc bootstrap on x86_64 linux. If a virtual register is copied to a physical register, it's not necessarily defined by a copy. We have to watch out it doesn't clobber any sub-register that might be live during its live interval. If the live interval crosses a basic block, then it's not safe to check with the less conservative check (by scanning uses and defs) because it's possible a sub-register might be live out of the block. 
llvm-svn: 62144
 2009-01-13 03:57:45 +00:00
Devang Patel
6d7fd4b913 Use DebugInfo interface to lower dbg_* intrinsics. 
llvm-svn: 62126
 2009-01-13 00:32:17 +00:00
Evan Cheng
5e17ea36e1 Fix PR3241: Currently EmitCopyFromReg emits a copy from the physical register to a virtual register unless it requires an expensive cross class copy. That means we are only treating "expensive to copy" register dependency as physical register dependency. 
Also future proof the scheduler to handle "normal" physical register dependencies. The code is not exercised yet.

llvm-svn: 62074
 2009-01-12 03:19:55 +00:00
Evan Cheng
47dfb8c719 This is a dup of pr2659.ll. 
llvm-svn: 62029
 2009-01-10 19:06:32 +00:00
Evan Cheng
411c48b7d2 Duplicated node may produce a non-physical register def. 
llvm-svn: 62015
 2009-01-09 22:44:02 +00:00
Evan Cheng
84945aba0b Add test case from PR2659. 
llvm-svn: 62006
 2009-01-09 21:01:31 +00:00
Dan Gohman
a707c0dafe PR2659 was fixed by r61847. Add the testcase as a regression test. 
llvm-svn: 61986
 2009-01-09 08:16:12 +00:00
Evan Cheng
a70ecc2f51 The coalescer does not coalesce a virtual register to a physical register if any of the physical register's sub-register live intervals overlaps with the virtual register. This is overly conservative. It prevents a extract_subreg from being coalesced away: 
v1024 = EDI  // not killed
      =
      = EDI

One possible solution is for the coalescer to examine the sub-register live intervals in the same manner as the physical register. Another possibility is to examine defs and uses (when needed) of sub-registers. Both solutions are too expensive. For now, look for "short virtual intervals" and scan instructions to look for conflict instead.

This is a small win on x86-64. e.g. It shaves 403.gcc by ~80 instructions.

llvm-svn: 61847
 2009-01-07 02:08:57 +00:00
Chris Lattner
f6de7aa2c9 add a testcase. 
llvm-svn: 61845
 2009-01-07 01:48:08 +00:00
Dan Gohman
ca4475dd7b Add patterns to match conditional moves with loads folded 
into their left operand, rather than their right. Do this
by commuting the operands and inverting the condition.

llvm-svn: 61842
 2009-01-07 01:00:24 +00:00
Dan Gohman
2682e8745c X86_COND_C and X86_COND_NC are alternate mnemonics for 
X86_COND_B and X86_COND_AE, respectively.

llvm-svn: 61835
 2009-01-07 00:15:08 +00:00