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Commit Graph

70607 Commits

Author SHA1 Message Date
Eric Christopher
27757a2e74 Remove commented out code.
llvm-svn: 211838
2014-06-27 01:27:05 +00:00
Eric Christopher
9095101a3e Remove extraneous parens and extraneous const cast (and fix the
prototype for the function to patch what we were returning).

llvm-svn: 211837
2014-06-27 01:27:03 +00:00
Eric Christopher
e0bc241533 Move the subtarget dependent features from the target machine to
the subtarget for the MSP430 target.

llvm-svn: 211836
2014-06-27 01:14:54 +00:00
Eric Christopher
b041717dce Remove uses and caches of the target machine and subtarget from
both MSP430InstrInfo and MSP430RegisterInfo. Remove unused member
variable StackAlign from MSP430RegisterInfo. Update constructors
accordingly.

llvm-svn: 211835
2014-06-27 01:14:50 +00:00
Eric Christopher
b69f775d9c Remove caching of an unused subtarget from MSP430FrameLowering.
llvm-svn: 211830
2014-06-27 00:52:11 +00:00
Adam Nemet
e14e099b2e [X86] AVX512: Add vbroadcasti*
For now I used a separate template for these sub-vector/tuple broadcasts
rather than sharing the mem variants with avx512_int_broadcast_rm.

<rdar://problem/17402869>

llvm-svn: 211828
2014-06-27 00:43:38 +00:00
Eric Christopher
50d95a165d Remove unnecessary caching of variables by MSP430TargetLowering and
make the constructor more general since it only needs a target
machine.

llvm-svn: 211827
2014-06-27 00:37:59 +00:00
Eric Christopher
3e999fe1f8 Have MSP430SelectionDAGInfo constructor take a DataLayout rather
than a target machine since it doesn't need anything past the
DataLayout.

llvm-svn: 211826
2014-06-27 00:37:57 +00:00
Eric Christopher
00fde1b2c4 Move all of the hexagon subtarget dependent variables from the target
machine to the subtarget.

llvm-svn: 211824
2014-06-27 00:27:40 +00:00
Eric Christopher
7e6b0397f7 Have HexagonSelectionDAGInfo take a DataLayout rather than a
target machine since that's all it needs.

llvm-svn: 211822
2014-06-27 00:18:25 +00:00
Eric Christopher
5fa6f29651 Make HexagonISelLowering not dependent upon a HexagonTargetMachine,
but a normal TargetMachine and remove a few cached uses.

llvm-svn: 211821
2014-06-27 00:13:52 +00:00
Eric Christopher
019229370a Reduce indentation.
llvm-svn: 211820
2014-06-27 00:13:49 +00:00
Eric Christopher
745c99219c Remove unnecessary caching of the subtarget for HexagonFrameLowering and remove the unused constructor argument.
llvm-svn: 211819
2014-06-27 00:13:47 +00:00
Eric Christopher
a43db9d719 InstrItineraryData is already on the subtarget, no reason to
cache it on the target as well.

llvm-svn: 211818
2014-06-27 00:13:43 +00:00
Juergen Ributzka
4e8c3d809f [StackMaps] Enable patchpoint liveness analysis per default.
llvm-svn: 211817
2014-06-26 23:39:52 +00:00
Juergen Ributzka
f24160ef4c [Stackmaps] Remove the liveness calculation for stackmap intrinsics.
There is no need to calculate the liveness information for stackmaps. The
liveness information is still available for the patchpoint intrinsic and
that is also the intended usage model.

Related to <rdar://problem/17473725>

llvm-svn: 211816
2014-06-26 23:39:44 +00:00
Lang Hames
ef8f18f9e4 [RuntimeDyld] Teach MachOObjectImage to deregister itself with the debugger upon
destruction the same way ELFObjectImage does.

llvm-svn: 211815
2014-06-26 23:05:44 +00:00
Alp Toker
97022b0c1f Revert "Introduce a string_ostream string builder facilty"
Temporarily back out commits r211749, r211752 and r211754.

llvm-svn: 211814
2014-06-26 22:52:05 +00:00
Eric Christopher
76f666eb23 Move the various Subtarget dependent members down to the subtarget
for the Sparc port. Use the same initializeSubtargetDependencies
function to handle initialization similar to the other ports to
handle dependencies.

llvm-svn: 211811
2014-06-26 22:33:55 +00:00
Eric Christopher
0092b3a0e7 Have SparcSelectionDAGInfo take a DataLayout to initialize since
that's all it needs.

llvm-svn: 211810
2014-06-26 22:33:52 +00:00
Eric Christopher
de87d01330 Remove the storage and use of the subtarget out of the sparc frame
lowering code.

llvm-svn: 211809
2014-06-26 22:33:50 +00:00
Arnold Schwaighofer
7e23314405 GVN: Preserve invariant.load metadata
If both instructions to be replaced are marked invariant the resulting
instruction is invariant.

rdar://13358910

Fix by Erik Eckstein!

llvm-svn: 211801
2014-06-26 19:51:19 +00:00
Eric Christopher
04713c650c Remove extraneous includes from the target machines.
llvm-svn: 211800
2014-06-26 19:30:05 +00:00
Eric Christopher
da2b8b72dd Move all of the ARM subtarget features down onto the subtarget
rather than the target machine.

llvm-svn: 211799
2014-06-26 19:30:02 +00:00
Eric Christopher
1272c4e1c4 Move the frame lowering constructors out of line to avoid circular
includes.

llvm-svn: 211798
2014-06-26 19:29:59 +00:00
Matt Arsenault
c2d6bb970a R600/SI: Add FP mode bits to binary.
The default rounding mode to initialize the mode register needs
to be reported to the runtime. Fill in other bits a kernel
may be interested in setting for future use.

llvm-svn: 211791
2014-06-26 17:22:30 +00:00
Aaron Ballman
a5cd4afa00 Silencing a warning about isZExtFree hiding an inherited virtual function. No functional change intended.
llvm-svn: 211783
2014-06-26 13:45:47 +00:00
Andrea Di Biagio
d30e61d81e Silence a warning due to a comparison between signed and unsigned.
No functional change intended.

llvm-svn: 211782
2014-06-26 13:41:10 +00:00
Will Schmidt
f6e2b6e4f5 Add support for ppc64/power8 as a host
llvm-svn: 211781
2014-06-26 13:37:03 +00:00
Will Schmidt
fbbc998175 add ppc64/pwr8 as target
includes handling DIR_PWR8 where appropriate
The P7Model Itinerary is currently tied in for use under the P8Model, and will be updated later.

llvm-svn: 211779
2014-06-26 13:36:19 +00:00
Renato Golin
9ca48ec4d1 Added parsing co-processor names starting with "cr"
Additional compliant GAS names for coprocessor register name
are enabled for all instruction with parameter MCK_CoprocReg:
LDC,LDC2,STC,STC2,CDP,CDP2,MCR,MCR2,MCRR,MCRR2,MRC,MRC2,MRRC,MRRC2

Patch by Andrey Kuharev.

llvm-svn: 211776
2014-06-26 13:10:53 +00:00
Andrea Di Biagio
3be8532e69 [X86] Improve the selection of SSE3/AVX addsub instructions.
This patch teaches the backend how to canonicalize a shuffle vectors
according to the rule:

 - (shuffle (FADD A, B), (FSUB A, B), Mask) ->
       (shuffle (FSUB A, -B), (FADD A, -B), Mask)

Where 'Mask' is:
  <0,5,2,7>            ;; for v4f32 and v4f64 shuffles.
  <0,3>                ;; for v2f64 shuffles.
  <0,9,2,11,4,13,6,15> ;; for v8f32 shuffles.

In general, ISel only knows how to pattern-match a canonical
'fadd + fsub + blendi' dag node sequence into an ADDSUB instruction.

This new rule allows to convert a non-canonical dag sequence into a
canonical one that will be matched by a single ADDSUB at ISel stage.

The idea of converting a non-canonical ADDSUB into a canonical one by
swapping the first two operands of the shuffle, and then negating the
second operand of the FADD and FSUB, was originally proposed by Hal Finkel.

llvm-svn: 211771
2014-06-26 10:45:21 +00:00
Dinesh Dwivedi
9d122cf780 This patch removed duplicate code for matching patterns
which are now handled in SimplifyUsingDistributiveLaws() 
(after r211261)

Differential Revision: http://reviews.llvm.org/D4253

llvm-svn: 211768
2014-06-26 08:57:33 +00:00
Dinesh Dwivedi
b98a2e9f49 Added instruction combine to transform few more negative values addition to subtraction (Part 2)
This patch enables transforms for

(x + (~(y | c) + 1)   -->   x - (y | c) if c is even

Differential Revision: http://reviews.llvm.org/D4209

llvm-svn: 211765
2014-06-26 05:40:22 +00:00
David Majnemer
96d60954b8 GlobalOpt: Don't optimize thread_local for initializers
Folding a reference to a thread_local variable into another global
variable's initializer is very problematic, there is no relocation that
exists to represent such an access.

llvm-svn: 211762
2014-06-26 03:02:19 +00:00
Matt Arsenault
435a7c1256 R600: Fix vector FMA
llvm-svn: 211757
2014-06-26 01:28:05 +00:00
Hans Wennborg
0b74da6314 Don't build switch tables for dllimport and TLS variables in GEPs
This is a follow-up to r211331, which failed to notice that we were
returning early from ValidLookupTableConstant for GEPs.

llvm-svn: 211753
2014-06-26 00:30:52 +00:00
Alp Toker
5ad6808be1 MSVC build fix following r211749
Avoid strndup()

llvm-svn: 211752
2014-06-26 00:25:41 +00:00
Adam Nemet
aa04918ad4 [X86] AVX512: Fix asm syntax for packed vcmp
The *_alt defs for vcmp are used by the InstParser (the asm string in the main
def is used by the InstPrinter) .  The former was accepting vector registers
as destination rather than mask registers.

llvm-svn: 211750
2014-06-26 00:21:12 +00:00
Alp Toker
fd9ead3b6f Introduce a string_ostream string builder facilty
string_ostream is a safe and efficient string builder that combines opaque
stack storage with a built-in ostream interface.

small_string_ostream<bytes> additionally permits an explicit stack storage size
other than the default 128 bytes to be provided. Beyond that, storage is
transferred to the heap.

This convenient class can be used in most places an
std::string+raw_string_ostream pair or SmallString<>+raw_svector_ostream pair
would previously have been used, in order to guarantee consistent access
without byte truncation.

The patch also converts much of LLVM to use the new facility. These changes
include several probable bug fixes for truncated output, a programming error
that's no longer possible with the new interface.

llvm-svn: 211749
2014-06-26 00:00:48 +00:00
Argyrios Kyrtzidis
2cce248daa For CrashRecoveryContext::RunSafelyOnThread, propagate Darwin's PRIO_DARWIN_BG to the new thread if it is
set on the calling thread.

This allows libclang's indexing threads to propagate their priority to the clang module building threads.

rdar://17459872

llvm-svn: 211747
2014-06-25 23:54:50 +00:00
Juergen Ributzka
97839af0ec [FastISel][X86] More refactoring of select lowering and XALU folding. NFC.
llvm-svn: 211740
2014-06-25 22:50:59 +00:00
Eric Christopher
ce17f76f37 The includes were sorted. Revert r210578.
llvm-svn: 211737
2014-06-25 22:36:37 +00:00
Juergen Ributzka
70d663743e [FastISel][X86] Refactor XALU folding. NFC.
llvm-svn: 211735
2014-06-25 22:17:23 +00:00
Juergen Ributzka
87fbbdf13d [FastISel][X86] Only fold the cmp into the select when both instructions are in the same basic block.
If the cmp is in a different basic block, then it is possible that not all
operands of that compare have defined registers. This can happen when one of
the operands to the cmp is a load and the load gets folded into the cmp. In
this case FastISel will skip the load instruction and the vreg is never
defined.

llvm-svn: 211730
2014-06-25 20:06:12 +00:00
Rafael Espindola
9eb4161123 Merge the used symbol scanning of MCObjectStreamer and RecordStreamer.
This completes the refactoring of RecordStreamer.

llvm-svn: 211727
2014-06-25 18:37:33 +00:00
David Blaikie
ac824331fd Revert "PR20038: DebugInfo: Inlined call sites where the caller has debug info but the call itself has no debug location."
This reverts commit r211723.

Breaks the ASan/compiler-rt build... guess I didn't test very far at all
:/.

llvm-svn: 211724
2014-06-25 18:20:54 +00:00
David Blaikie
59345c0fdc PR20038: DebugInfo: Inlined call sites where the caller has debug info but the call itself has no debug location.
This situation does bad things when inlined, so I've fixed Clang not to
produce inlinable call sites without locations when the caller has debug
info (in the one case where I could find that this occurred). This
updates the PR20038 test case to be what clang now produces, and readds
the assertion that had to be removed due to this bug.

I've also beefed up the debug info verifier to help diagnose these
issues in the future, and I hope to add checks to the inliner to just
assert-fail if it encounters this situation. If, in the future, we
decide we have to cope with this situation, the right thing to do is
probably to just remove all the DebugLocs from the inlined instructions.

llvm-svn: 211723
2014-06-25 18:03:10 +00:00
Tyler Nowicki
feb5a3355b Add Rpass-missed and Rpass-analysis reports to the loop vectorizer. The remarks give the vector width of vectorized loops and a brief analysis of loops that fail to be vectorized. For example, an analysis will be generated for loops containing control flow that cannot be simplified to a select. The optimization remarks also give the debug location of expressions that cannot be vectorized, for example the location of an unvectorizable call.
Reviewed by: Arnold Schwaighofer

llvm-svn: 211721
2014-06-25 17:50:15 +00:00
Andrea Di Biagio
de7985179f [X86] Always prefer to lower a VECTOR_SHUFFLE into a BLENDI instead of SHUFP (or VPERM2X128).
This patch teaches method 'LowerVECTOR_SHUFFLE' to give higher precedence to
the check for 'isBlendMask'; the idea is that, when possible, we should firstly
check if a shuffle performs a blend, and in case, try to lower it into a BLENDI
instead of selecting a SHUFP or (worse) a VPERM2X128.

In general:
 - AVX VBLENDPS/D always have better latency and throughput than VPERM2F128;
 - BLENDPS/D instructions tend to always have better 'reciprocal throughput'
   than the equivalent SHUFPS/D;
 - Both BLENDPS/D and SHUFPS/D are often decoded into the same number of
   m-ops; however, a m-op obtained from a BLENDPS/D can be scheduled to more
   than one execution port.

This patch:
 - Moves the check for 'isBlendMask' immediately before the check for
   'isSHUFPMask' within method 'LowerVECTOR_SHUFFLE';
 - Updates existing tests for sse/avx shuffle/blend instructions to verify
   that we select (v)blendps/d when possible (instead of (v)shufps/d or
   vperm2f128).

llvm-svn: 211720
2014-06-25 17:41:58 +00:00