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Commit Graph

151 Commits

Author SHA1 Message Date
Chandler Carruth
a490793037 Use the new script to sort the includes of every file under lib.
Sooooo many of these had incorrect or strange main module includes.
I have manually inspected all of these, and fixed the main module
include to be the nearest plausible thing I could find. If you own or
care about any of these source files, I encourage you to take some time
and check that these edits were sensible. I can't have broken anything
(I strictly added headers, and reordered them, never removed), but they
may not be the headers you'd really like to identify as containing the
API being implemented.

Many forward declarations and missing includes were added to a header
files to allow them to parse cleanly when included first. The main
module rule does in fact have its merits. =]

llvm-svn: 169131
2012-12-03 16:50:05 +00:00
Chad Rosier
528b5cd1a6 [inline asm] Implement mayLoad and mayStore for inline assembly. In general,
the MachineInstr MayLoad/MayLoad flags are based on the tablegen implementation.
For inline assembly, however, we need to compute these based on the constraints.

Revert r166929 as this is no longer needed, but leave the test case in place. 
rdar://12033048 and PR13504

llvm-svn: 167040
2012-10-30 19:11:54 +00:00
Jakob Stoklund Olesen
bf5a17c340 Remove unused BitVectors from getAllocatableSet().
llvm-svn: 165999
2012-10-16 00:05:06 +00:00
Jakob Stoklund Olesen
56bb584754 Switch most getReservedRegs() clients to the MRI equivalent.
Using the cached bit vector in MRI avoids comstantly allocating and
recomputing the reserved register bit vector.

llvm-svn: 165983
2012-10-15 21:57:41 +00:00
Roman Divacky
85348270cd Stop casting away const qualifier needlessly.
llvm-svn: 163258
2012-09-05 22:26:57 +00:00
Jakob Stoklund Olesen
ef5dcf47b8 Move tie checks into MachineVerifier::visitMachineOperand.
llvm-svn: 163152
2012-09-04 18:38:28 +00:00
Jakob Stoklund Olesen
efc28b164d Verify the consistency of inline asm operands.
The operands on an INLINEASM machine instruction are divided into groups
headed by immediate flag operands. Verify this structure.

Extract verifyTiedOperands(), and only call it for non-inlineasm
instructions.

llvm-svn: 162849
2012-08-29 18:11:05 +00:00
Jakob Stoklund Olesen
6137bd2af6 Verify the tied operand flags.
WHen running with -verify-machineinstrs, check that tied operands come
in matching use/def pairs, and that they are consistent with MCInstrDesc
when it applies.

llvm-svn: 162816
2012-08-29 00:38:03 +00:00
Craig Topper
d66ff79b2c Add a getName function to MachineFunction. Use it in places that previously did getFunction()->getName(). Remove includes of Function.h that are no longer needed.
llvm-svn: 162347
2012-08-22 06:07:19 +00:00
Jakob Stoklund Olesen
a3264c242c Don't add CFG edges for redundant conditional branches.
IR that hasn't been through SimplifyCFG can look like this:

  br i1 %b, label %r, label %r

Make sure we don't create duplicate Machine CFG edges in this case.

Fix the machine code verifier to accept conditional branches with a
single CFG edge.

llvm-svn: 162230
2012-08-20 21:39:52 +00:00
Jakob Stoklund Olesen
698d32d8c4 Add CFG checks to MachineVerifier.
Verify that the predecessor and successor lists are consistent and free
of duplicates.

llvm-svn: 162223
2012-08-20 20:52:06 +00:00
Richard Smith
e3b0fbab8a Fix undefined behavior: don't perform array indexing through a potentially null
pointer.

llvm-svn: 161919
2012-08-15 01:39:31 +00:00
Jakob Stoklund Olesen
4be65d0d0c Verify regunit intervals along with virtreg intervals.
Don't cause regunit intervals to be computed just to verify them. Only
check the already cached intervals.

llvm-svn: 161183
2012-08-02 16:36:50 +00:00
Jakob Stoklund Olesen
802cd7688f Add report() functions that take a LiveInterval argument.
llvm-svn: 161178
2012-08-02 14:31:49 +00:00
Jakob Stoklund Olesen
5848ce22b0 Extract some methods from verifyLiveIntervals.
No functional change.

llvm-svn: 161149
2012-08-02 00:20:20 +00:00
Jakob Stoklund Olesen
85840cd877 Also verify RegUnit intervals at uses.
llvm-svn: 161147
2012-08-01 23:52:40 +00:00
Jakob Stoklund Olesen
45755341ad Verify two-address constraints more carefully.
Include <undef> operands and virtual registers after leaving SSA form.

llvm-svn: 160734
2012-07-25 16:49:11 +00:00
Pete Cooper
4a544942c5 Fix crash in machine verifier when trying to print the def of a register which has no def
llvm-svn: 160531
2012-07-19 23:40:38 +00:00
Bill Wendling
343eebdbe4 Remove tabs.
llvm-svn: 160475
2012-07-19 00:04:14 +00:00
Jakob Stoklund Olesen
3199cf0fda Check for extra kill flags on live-out virtual registers.
This would previously get reported as the misleading "Virtual register
def doesn't dominate all uses."

llvm-svn: 159460
2012-06-29 21:00:00 +00:00
Jakob Stoklund Olesen
cc79c28e91 Enforce stricter liveness rules for PHIs.
Verify that all paths from the entry block to a virtual register read
pass through a def. Enable this check even when MRI->isSSA() is false.

Verify that the live range of a virtual register is live out of all
predecessor blocks, even for PHI-values.

This requires that PHIElimination sometimes inserts IMPLICIT_DEF
instruction in predecessor blocks.

llvm-svn: 159150
2012-06-25 18:18:27 +00:00
Jakob Stoklund Olesen
f3226a960c Also verify the def index for early clobbers.
llvm-svn: 159039
2012-06-22 22:23:58 +00:00
Jakob Stoklund Olesen
f3deae3d2f Fix some more LiveInterval enumerations.
Deterministically enumerate the virtual registers instead.

llvm-svn: 158872
2012-06-20 23:23:59 +00:00
Akira Hatanaka
93c5168e49 Make machine verifier check the first instruction of the last bundle instead of
the last instruction of a basic block.

llvm-svn: 158468
2012-06-14 20:51:13 +00:00
Pete Cooper
089cb1dcc5 Move terminator machine verification to check MachineBasicBlock::instr_iterator instead of MBB::iterator
llvm-svn: 158154
2012-06-07 17:41:39 +00:00
Jakob Stoklund Olesen
5dbcc6898b Properly verify liveness with bundled machine instructions.
Bundles should be treated as one atomic transaction when checking
liveness. That is how the register allocator (and VLIW targets) treats
bundles.

llvm-svn: 158116
2012-06-06 22:34:30 +00:00
Jakob Stoklund Olesen
be0b8939c0 Switch all register list clients to the new MC*Iterator interface.
No functional change intended.

Sorry for the churn. The iterator classes are supposed to help avoid
giant commits like this one in the future. The TableGen-produced
register lists are getting quite large, and it may be necessary to
change the table representation.

This makes it possible to do so without changing all clients (again).

llvm-svn: 157854
2012-06-01 23:28:30 +00:00
Evan Cheng
bfbc51bb8f Optional def can be either a def or a use (of reg0).
llvm-svn: 157640
2012-05-29 19:40:44 +00:00
Jakob Stoklund Olesen
0069dd0862 Fix a verifier bug.
Make sure useless (def-only) intervals also get verified.

llvm-svn: 157000
2012-05-17 18:32:40 +00:00
Jakob Stoklund Olesen
cc0cf22b98 Add an MF argument to TRI::getPointerRegClass() and TII::getRegClass().
The getPointerRegClass() hook can return register classes that depend on
the calling convention of the current function (ptr_rc_tailcall).

So far, we have been able to infer the calling convention from the
subtarget alone, but as we add support for multiple calling conventions
per target, that no longer works.

Patch by Yiannis Tsiouris!

llvm-svn: 156328
2012-05-07 22:10:26 +00:00
Jakob Stoklund Olesen
4b4ee58c4c Enable machine code verification after PreSched2 passes.
The late scheduler depends on accurate liveness information if it is
breaking anti-dependencies, so we should be able to verify it.

Relax the terminator checking in the machine code verifier so it can
handle the basic blocks created by if conversion.

llvm-svn: 153614
2012-03-28 23:31:15 +00:00
Jakob Stoklund Olesen
37927fe83c Skip liveness verification when MRI->tracksLiveness() is false.
Extract the liveness verification into its own method.

This makes it possible to run the machine code verifier after liveness
information is no longer required to be valid.

llvm-svn: 153596
2012-03-28 20:47:35 +00:00
Jakob Stoklund Olesen
ee9a75c67f Report the defining instruction.
llvm-svn: 152460
2012-03-10 00:44:11 +00:00
Jakob Stoklund Olesen
5c3128acf6 Add SSA verification to MachineVerifier.
Somehow we never verified SSA dominance before.

llvm-svn: 152458
2012-03-10 00:36:06 +00:00
Jakob Stoklund Olesen
5c58e991c5 Use SmallPtrSet instead of DenseSet.
llvm-svn: 152457
2012-03-10 00:36:04 +00:00
Craig Topper
a95d527c6a Convert more GenRegisterInfo tables from unsigned to uint16_t to reduce static data size.
llvm-svn: 152016
2012-03-05 05:37:41 +00:00
Jakob Stoklund Olesen
55ff251cc1 Move the operand iterator into MachineInstrBundle.h where it belongs.
Extract a base class and provide four specific sub-classes for iterating
over const/non-const bundles/instructions.

This eliminates the mystery bool constructor argument.

llvm-svn: 151684
2012-02-29 00:33:41 +00:00
Jakob Stoklund Olesen
e3a308c116 Handle regmasks in the machine code verifier.
llvm-svn: 151607
2012-02-28 01:42:41 +00:00
Jakob Stoklund Olesen
edc3446412 Update machine code verifier.
After the SlotIndex slot names were updated, it is possible to apply
stricter checks to live intervals.

Also treat bundles as bags of operands when checking live intervals.

llvm-svn: 151531
2012-02-27 18:24:30 +00:00
Lang Hames
e470bbc589 Update MachineVerifier to check the new physreg live-in rules.
llvm-svn: 150496
2012-02-14 19:17:48 +00:00
Evan Cheng
68ba5536f3 - Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function
to finalize MI bundles (i.e. add BUNDLE instruction and computing register def
  and use lists of the BUNDLE instruction) and a pass to unpack bundles.
- Teach more of MachineBasic and MachineInstr methods to be bundle aware.
- Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to
  prevent IT blocks from being broken apart.

llvm-svn: 146542
2011-12-14 02:11:42 +00:00
Evan Cheng
1acd685d87 Add bundle aware API for querying instruction properties and switch the code
generator to it. For non-bundle instructions, these behave exactly the same
as the MC layer API.

For properties like mayLoad / mayStore, look into the bundle and if any of the
bundled instructions has the property it would return true.
For properties like isPredicable, only return true if *all* of the bundled
instructions have the property.
For properties like canFoldAsLoad, isCompare, conservatively return false for
bundles.

llvm-svn: 146026
2011-12-07 07:15:52 +00:00
Benjamin Kramer
a2f57dee6d Remove all remaining uses of Value::getNameStr().
llvm-svn: 144648
2011-11-15 16:27:03 +00:00
Jakob Stoklund Olesen
25e009690c Use getVNInfoBefore() when it makes sense.
llvm-svn: 144517
2011-11-14 01:39:36 +00:00
Jakob Stoklund Olesen
9b34607bdf Rename SlotIndexes to match how they are used.
The old naming scheme (load/use/def/store) can be traced back to an old
linear scan article, but the names don't match how slots are actually
used.

The load and store slots are not needed after the deferred spill code
insertion framework was deleted.

The use and def slots don't make any sense because we are using
half-open intervals as is customary in C code, but the names suggest
closed intervals.  In reality, these slots were used to distinguish
early-clobber defs from normal defs.

The new naming scheme also has 4 slots, but the names match how the
slots are really used.  This is a purely mechanical renaming, but some
of the code makes a lot more sense now.

llvm-svn: 144503
2011-11-13 20:45:27 +00:00
Jakob Stoklund Olesen
153f593870 Fix sub-register operand verification.
PhysReg operands are not allowed to have sub-register indices at all.

For virtual registers with sub-reg indices, check that all registers in
the register class support the sub-reg index.

llvm-svn: 141220
2011-10-05 22:12:57 +00:00
Jakob Stoklund Olesen
bc6ae70907 Verify that terminators follow non-terminators.
This exposes a -segmented-stacks bug.

llvm-svn: 140429
2011-09-23 22:45:39 +00:00
Andrew Trick
c94573ded6 Lower ARM adds/subs to add/sub after adding optional CPSR operand.
This is still a hack until we can teach tblgen to generate the
optional CPSR operand rather than an implicit CPSR def. But the
strangeness is now limited to the selection DAG. ADD/SUB MI's no
longer have implicit CPSR defs, nor do we allow flag setting variants
of these opcodes in machine code. There are several corner cases to
consider, and getting one wrong would previously lead to nasty
miscompilation. It's not the first time I've debugged one, so this
time I added enough verification to ensure it won't happen again.

llvm-svn: 140228
2011-09-21 02:20:46 +00:00
Jakob Stoklund Olesen
83f23f23cd Stop verifying hasPHIKill() flags.
There is only one legitimate use remaining, in addIntervalsForSpills().
All other calls to hasPHIKill() are only used to update PHIKill flags.

The addIntervalsForSpills() function is part of the old spilling
framework, only used by linearscan.

llvm-svn: 139783
2011-09-15 05:16:30 +00:00
Jakob Stoklund Olesen
0f099a3c58 Revert "Don't check liveness of unallocatable registers."
The ARM target depends on CPSR liveness being tracked after register
allocation.

llvm-svn: 136548
2011-07-30 00:57:25 +00:00