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80 Commits

Author SHA1 Message Date
Chris Lattner
7d8093efb1 No really, these are dead now 
llvm-svn: 14145
 2004-06-11 04:50:14 +00:00
Chris Lattner
a8e603b719 Now that compare instructions aren't lumped in with the other twoargfp instructions, 
we can get rid of the FpUCOM/FpUCOMi pseudo instructions, which makes stuff simpler
and faster.

llvm-svn: 14144
 2004-06-11 04:49:02 +00:00
Chris Lattner
b050f778ca Introduce a new FP instruction type to separate the compare cases from the 
twoarg cases.

llvm-svn: 14143
 2004-06-11 04:41:24 +00:00
Chris Lattner
4c8b57ea31 Add support for the setp instructions 
llvm-svn: 14140
 2004-06-11 04:30:06 +00:00
Chris Lattner
15ac62827e Add immediate forms of in/out. Use let to shorten lines 
llvm-svn: 12895
 2004-04-13 17:19:31 +00:00
Chris Lattner
43f754339a Fix issues that the local allocator has dealing with instructions that implicitly use ST(0) 
llvm-svn: 12855
 2004-04-12 03:02:48 +00:00
Chris Lattner
9cdc472518 No really, fix printing for LLC. I gotta get a way for CVS to whine at me if 
I have unsaved emacs buffers, geeze...

llvm-svn: 12854
 2004-04-12 01:52:04 +00:00
Chris Lattner
f1d59be0e8 Correct printing for LLC and the encoding for the JIT 
llvm-svn: 12853
 2004-04-12 01:50:04 +00:00
Chris Lattner
cfb7144bf1 Add two new instructions 
llvm-svn: 12850
 2004-04-12 01:38:55 +00:00
Chris Lattner
dda382531e Add some new instructions 
llvm-svn: 12838
 2004-04-11 20:24:15 +00:00
John Criswell
8740c3767d Changes recommended by Chris: 
InstSelectSimple.cpp:
  Change the checks for proper I/O port address size into an exit() instead
  of an assertion.  Assertions aren't used in Release builds, and handling
  this error should be graceful (not that this counts as graceful, but it's
  more graceful).

  Modified the generation of the IN/OUT instructions to have 0 arguments.
X86InstrInfo.td:
  Added the OpSize attribute to the 16 bit IN and OUT instructions.

llvm-svn: 12786
 2004-04-08 22:39:13 +00:00
John Criswell
f6b16ea70b Added the llvm.readport and llvm.writeport intrinsics for x86. These do 
I/O port instructions on x86.  The specific code sequence is tailored to
the parameters and return value of the intrinsic call.
Added the ability for implicit defintions to be printed in the Instruction
Printer.
Added the ability for RawFrm instruction to print implict uses and
defintions with correct comma output.  This required adjustment to some
methods so that a leading comma would or would not be printed.

llvm-svn: 12782
 2004-04-08 20:31:47 +00:00
Chris Lattner
993d6106c7 Fix incorrect encoding of some ADC and SBB instuctions 
llvm-svn: 12710
 2004-04-06 19:20:32 +00:00
Chris Lattner
e84f12a165 The sbb instructions really ARE sbb's, not adc's 
llvm-svn: 12682
 2004-04-06 02:02:11 +00:00
Alkis Evlogimenos
85e007a6dc Fix type in comments 
llvm-svn: 12611
 2004-04-02 16:02:50 +00:00
Alkis Evlogimenos
20b074682c Add more ADC and SBB variants 
llvm-svn: 12607
 2004-04-02 07:11:10 +00:00
Chris Lattner
e4fa3010db Add FP conditional move instructions, which annoyingly have special properties 
that require the asmwriter to be extended (printing implicit uses before the
explicit operands)

llvm-svn: 12574
 2004-03-31 22:02:13 +00:00
Chris Lattner
57968a98df Fix some serious bugs in the cmov descriptions, which didn't cause a problem because 
we never generated them

Make indentation a bit more consistent

llvm-svn: 12549
 2004-03-30 20:18:02 +00:00
Alkis Evlogimenos
6ac147a7fb Add LAHF instruction 
llvm-svn: 12424
 2004-03-15 17:20:14 +00:00
Alkis Evlogimenos
da990ad8a4 Add support for a wider range of CMOV instructions. 
llvm-svn: 12336
 2004-03-12 17:59:56 +00:00
Alkis Evlogimenos
7c0224327e Differentiate between extended precision floats (80-bit) and double precision floats (64-bit) 
llvm-svn: 12254
 2004-03-09 03:37:54 +00:00
Alkis Evlogimenos
65649a50e9 Add memory operand version of conditional move. 
llvm-svn: 12190
 2004-03-07 03:19:11 +00:00
Alkis Evlogimenos
8d8f872b3d Use correct template for SHLD and SHRD instructions so that the memory 
operand size is correctly specified.

llvm-svn: 11997
 2004-02-29 09:19:40 +00:00
Alkis Evlogimenos
7ecfe0a839 A big X86 instruction rename. The instructions are renamed to make 
their names more decriptive. A name consists of the base name, a
default operand size followed by a character per operand with an
optional special size. For example:

ADD8rr -> add, 8-bit register, 8-bit register

IMUL16rmi -> imul, 16-bit register, 16-bit memory, 16-bit immediate

IMUL16rmi8 -> imul, 16-bit register, 16-bit memory, 8-bit immediate

MOVSX32rm16 -> movsx, 32-bit register, 16-bit memory

llvm-svn: 11995
 2004-02-29 08:50:03 +00:00
Alkis Evlogimenos
0f96b44e0e Use correct template for ADC instruction with memory operands. 
llvm-svn: 11974
 2004-02-29 02:18:17 +00:00
Alkis Evlogimenos
6815402082 SHLD and SHRD take 32-bit operands but an 8-bit immediate. Rename them 
to denote this fact.

llvm-svn: 11972
 2004-02-28 23:46:44 +00:00
Alkis Evlogimenos
e8dac99a43 Floating point loads/stores act on memory operands. Rename them to 
denote this fact.

llvm-svn: 11971
 2004-02-28 23:42:35 +00:00
Alkis Evlogimenos
1d71a15be9 Rename instruction templates to be easier to the human eye to 
parse. The name is now I (operand size)*. For example:

Im32 -> instruction with 32-bit memory operands.

Im16i8 -> instruction with 16-bit memory operands and 8 bit immediate
          operands.

llvm-svn: 11970
 2004-02-28 23:09:03 +00:00
Alkis Evlogimenos
f208a0fd81 Each instruction now has both an ImmType and a MemType. This describes 
the size of the immediate and the memory operand on instructions that
use them. This resolves problems with instructions that take both a
memory and an immediate operand but their sizes differ (i.e. ADDmi32b).

llvm-svn: 11967
 2004-02-28 22:02:05 +00:00
Alkis Evlogimenos
977dbaadf7 Do not generate instructions with mismatched memory/immediate sized 
operands. The X86 backend doesn't handle them properly right now.

llvm-svn: 11944
 2004-02-28 06:01:43 +00:00
Alkis Evlogimenos
84f00e93f7 Further comment updates. 
llvm-svn: 11933
 2004-02-28 03:20:31 +00:00
Alkis Evlogimenos
edbe362160 Update comments. 
llvm-svn: 11932
 2004-02-28 03:12:31 +00:00
Alkis Evlogimenos
0f91ce52a0 My previous commit broke the jit. The shift instructions always take 
an 8-bit immediate. So mark the shifts that take immediates as taking
an 8-bit argument. The rest with the implicit use of CL are marked
appropriately.

A bug still exists:

def SHLDmri32  : I2A8 <"shld", 0xA4, MRMDestMem>, TB;           // [mem32] <<= [mem32],R32 imm8

The immediate in the above instruction is 8-bit but the memory
reference is 32-bit. The printer prints this as an 8-bit reference
which confuses the assembler. Same with SHRDmri32.

llvm-svn: 11931
 2004-02-28 02:56:26 +00:00
Alkis Evlogimenos
ace6d81654 Fix argument size for SHL, SHR, SAR, SHLD and SHRD families of 
instructions.

llvm-svn: 11923
 2004-02-27 19:46:30 +00:00
Alkis Evlogimenos
839c70f45d Fix encoding of ADD and SUB family of instructions. Also rearrange 
them so that they are consistent with AND, XOR, etc...

llvm-svn: 11922
 2004-02-27 18:57:00 +00:00
Alkis Evlogimenos
56d357aa23 Rename MRMS[0-7]{r,m} to MRM[0-7]{r,m}. 
llvm-svn: 11921
 2004-02-27 18:55:12 +00:00
Alkis Evlogimenos
5ac109957f Add memory operand folding support for the SETcc family of 
instructions.

llvm-svn: 11907
 2004-02-27 16:13:37 +00:00
Alkis Evlogimenos
0742b93bb9 Add memory operand folding support for SHLD and SHRD instructions. 
llvm-svn: 11905
 2004-02-27 15:03:18 +00:00
Alkis Evlogimenos
b1f67f6741 Add memory operand folding support for SHL, SHR and SAR, SHLD instructions. 
llvm-svn: 11903
 2004-02-27 09:28:43 +00:00
Alkis Evlogimenos
cf49d13ed2 Rename SHL, SHR, SAR, SHLD and SHLR instructions to make them 
consistent with the rest and also pepare for the addition of their
memory operand variants.

llvm-svn: 11902
 2004-02-27 06:57:05 +00:00
Chris Lattner
f9acb33dfd Add a new cmove instruction 
llvm-svn: 11722
 2004-02-23 01:16:05 +00:00
Alkis Evlogimenos
7ec1bad952 Fix argument size for MOVSX and MOVZX instructions. 
llvm-svn: 11576
 2004-02-18 16:20:40 +00:00
Alkis Evlogimenos
c6f0651e5c These store to memory too. 
llvm-svn: 11558
 2004-02-17 17:53:48 +00:00
Chris Lattner
88271db3bc These store to memory, not read from it. 
llvm-svn: 11556
 2004-02-17 17:46:50 +00:00
Alkis Evlogimenos
b815fd46ec Add TEST and XCHG memory operand support. 
llvm-svn: 11550
 2004-02-17 15:48:42 +00:00
Alkis Evlogimenos
32a5b0fd6c Add OR and XOR memory operand support. 
llvm-svn: 11549
 2004-02-17 15:33:14 +00:00
Alkis Evlogimenos
135c4faa55 Add memory operand folding support for MUL, DIV, IDIV, NEG, NOT, 
MOVSX, and MOVZX.

llvm-svn: 11546
 2004-02-17 09:14:23 +00:00
Alkis Evlogimenos
d7e3cc8d65 Add CMP{rm,mr,mi}{8,16,32}, INCm{8,16,32} and DECm{8,16,32} instructions. 
llvm-svn: 11544
 2004-02-17 08:49:00 +00:00
Alkis Evlogimenos
638db7b5aa Add SUB{rm,mr,mi}{8,16,32} instructions. 
llvm-svn: 11543
 2004-02-17 08:17:40 +00:00
Alkis Evlogimenos
28691e063b Add support for ADC{rm.mr}32 and SBB{rm,mr}32. 
llvm-svn: 11540
 2004-02-17 08:06:31 +00:00