RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2025-02-01 05:01:59 +01:00
Code Issues Projects Releases Wiki Activity
150,989 Commits 4 Branches 5 Tags
Commit Graph

2 Commits

Author SHA1 Message Date
Nirav Dave
28417300e7 [DAG] Rewrite areNonVolatileConsecutiveLoads to use BaseIndexOffset 
As discussed in D34087, rewrite areNonVolatileConsecutiveLoads using
generic checks. Also, propagate missing local handling from there to
BaseIndexOffset checks.

Tests of note:

  * test/CodeGen/X86/build-vector* - Improved.
  * test/CodeGen/BPF/undef.ll - Improved store alignment allows an
    additional store merge

  * test/CodeGen/X86/clear_upper_vector_element_bits.ll - This is a
    case we already do not handle well. Here, the DAG is improved, but
    scheduling causes a code size degradation.

Reviewers: RKSimon, craig.topper, spatel, andreadb, filcab

Subscribers: nemanjai, llvm-commits

Differential Revision: https://reviews.llvm.org/D34472

llvm-svn: 306819
 2017-06-30 12:23:41 +00:00
Simon Pilgrim
518fb821e4 [X86][SSE] Add 128/256/512 bit vector build vector from register tests 
llvm-svn: 302243
 2017-05-05 15:36:31 +00:00