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Commit Graph

78134 Commits

Author SHA1 Message Date
Chad Rosier
2673f8862f When fast iseling a GEP, accumulate the offset rather than emitting a series of
ADDs.  MaxOffs is used as a threshold to limit the size of the offset. Tradeoffs
being: (1) If we can't materialize the large constant then we'll cause fast-isel
to bail. (2) Too large of an offset can't be directly encoded in the ADD
resulting in a MOV+ADD.  Generally not a bad thing because otherwise we would
have had ADD+ADD, but on Thumb this turns into a MOVS+MOVT+ADD. Working on a fix
for that. (3) Conversely, too low of a threshold we'll miss opportunities to 
coalesce ADDs.
rdar://10412592

llvm-svn: 144886
2011-11-17 07:15:58 +00:00
Craig Topper
4d39196041 Remove seemingly unnecessary duplicate VROUND definitions.
llvm-svn: 144885
2011-11-17 07:04:00 +00:00
Chris Lattner
e368a7be33 x86/windows issues fixed.
llvm-svn: 144878
2011-11-17 01:42:23 +00:00
Eli Friedman
d02d82d355 Add support for custom names for library functions in TargetLibraryInfo. Add a custom name for fwrite and fputs on x86-32 OSX. Make SimplifyLibCalls honor the custom
names for fwrite and fputs.

Fixes <rdar://problem/9815881>.

llvm-svn: 144876
2011-11-17 01:27:36 +00:00
Daniel Dunbar
50227df250 llvm-build: Attempt to work around a CMake Makefile generator bug that doesn't
properly quote strings when writing the CMakeFiles/Makefile.cmake output file
(which lists the dependencies). This shows up when using CMake + MSYS Makefile
generator.

llvm-svn: 144873
2011-11-17 01:19:53 +00:00
Chad Rosier
c9ed1d9072 Don't unconditionally set the kill flag.
rdar://10456186

llvm-svn: 144872
2011-11-17 01:16:53 +00:00
Eli Friedman
1b0e97d7ab Turn on vzeroupper insertion on call boundaries for AVX; it works as far as I know, and I'd like to see wider testing.
llvm-svn: 144867
2011-11-17 00:21:52 +00:00
Daniel Dunbar
4affd889a2 build/make/test: Get rid of unused BUGPOINT_TOPTS variable.
llvm-svn: 144864
2011-11-16 23:56:03 +00:00
Eli Friedman
51adc2ea5a Make sure to replace the chain properly when DAGCombining a LOAD+EXTRACT_VECTOR_ELT into a single LOAD. Fixes PR10747/PR11393.
llvm-svn: 144863
2011-11-16 23:50:22 +00:00
Michael J. Spencer
346238dcfc Object/COFF: Support common symbols.
llvm-svn: 144861
2011-11-16 23:36:12 +00:00
Jim Grosbach
1b837af2bd Remove obsolete test.
The PLD encoding is checked via the .s file now.

llvm-svn: 144853
2011-11-16 22:50:38 +00:00
Jim Grosbach
fe5f0cfa29 Generalize the fixup info for ARM mode.
We don't (yet) have the granularity in the fixups to be specific about which
bitranges are affected. That's a future cleanup, but we're not there yet.

llvm-svn: 144852
2011-11-16 22:48:37 +00:00
Jim Grosbach
8fae277866 Update test for r144842.
llvm-svn: 144851
2011-11-16 22:46:27 +00:00
Akira Hatanaka
4068c25521 Lower 64-bit constant pool node.
llvm-svn: 144849
2011-11-16 22:44:38 +00:00
Akira Hatanaka
5f347432ca Lower 64-bit block address.
llvm-svn: 144847
2011-11-16 22:42:10 +00:00
Jim Grosbach
a14a3d22b1 Fix encoding of NOP used for padding in ARM mode .align.
llvm-svn: 144842
2011-11-16 22:40:25 +00:00
Akira Hatanaka
ca79236173 Add patterns for 64-bit tglobaladdr, tblockaddress, tjumptable and tconstpool
nodes.

llvm-svn: 144841
2011-11-16 22:39:56 +00:00
Akira Hatanaka
bb56ec5caf 64-bit jump register instruction.
llvm-svn: 144840
2011-11-16 22:36:01 +00:00
Evan Cheng
5bae2333cb Another missing X86ISD::MOVLPD pattern. rdar://10450317
llvm-svn: 144839
2011-11-16 22:24:44 +00:00
Jim Grosbach
8c8d091ecc ARM assembly parsing for shifted register operands for MOV instruction.
llvm-svn: 144837
2011-11-16 21:50:05 +00:00
Jim Grosbach
6007a95d57 Clean up debug printing of ARM shifted operands.
llvm-svn: 144836
2011-11-16 21:46:50 +00:00
Chad Rosier
36cc01dbd3 Add fast-isel stats to determine who's doing all the work, the
target-independent selector or the target-specific selector.

llvm-svn: 144833
2011-11-16 21:05:28 +00:00
Chad Rosier
bf857d6eaa Fix the stats collection for fast-isel. The failed count was only accounting
for a single miss and not all predecessor instructions that get selected by
the selection DAG instruction selector.  This is still not exact (e.g., over
states misses when folded/dead instructions are present), but it is a step in
the right direction.

llvm-svn: 144832
2011-11-16 21:02:08 +00:00
Chandler Carruth
ecf9ebbc72 There are already problems with building LLVM under VS2005, and it's
quite old now. Update the documentation to reflect this, and direct
people to use VS2008 or newer.

llvm-svn: 144818
2011-11-16 19:52:13 +00:00
Jim Grosbach
e9b1f2aead ARM assmebly two operand forms for LSR, ASR, LSL, ROR register.
llvm-svn: 144814
2011-11-16 19:12:24 +00:00
Jim Grosbach
18844fca8d ARM assembly parsing for RRX mnemonic.
rdar://9704684

llvm-svn: 144812
2011-11-16 19:05:59 +00:00
Pete Cooper
4f4a9794b2 Added missing comment about new custom lowering of DEC64
llvm-svn: 144811
2011-11-16 19:03:23 +00:00
Evan Cheng
5242b6aaa1 Disable expensive two-address optimizations at -O0. rdar://10453055
llvm-svn: 144806
2011-11-16 18:44:48 +00:00
Chad Rosier
69f9c432a6 Check to make sure we can select the instruction before trying to put the
operands into a register.  Otherwise, we may materialize dead code.

llvm-svn: 144805
2011-11-16 18:39:44 +00:00
Evan Cheng
cbfacfdb63 Disable the assertion again. Looks like fastisel is still generating bad kill markers.
llvm-svn: 144804
2011-11-16 18:32:14 +00:00
Jim Grosbach
acb7c2d555 ARM mode aliases for bitwise instructions w/ register operands.
rdar://9704684

llvm-svn: 144803
2011-11-16 18:31:45 +00:00
Bob Wilson
70092e2b0a Fix tablegen warning: hasSideEffects is inferred for eh_sjlj_dispatchsetup.
llvm-svn: 144798
2011-11-16 17:09:59 +00:00
NAKAMURA Takumi
9a0c941fff lib/Target/ARM/CMakeLists.txt: Disable optimization in ARMISelLowering.cpp also on MSC15(aka VS9). Seems miscompiled.
llvm-svn: 144794
2011-11-16 09:18:28 +00:00
Evan Cheng
2b239cbcf6 Sink codegen optimization level into MCCodeGenInfo along side relocation model
and code model. This eliminates the need to pass OptLevel flag all over the
place and makes it possible for any codegen pass to use this information.

llvm-svn: 144788
2011-11-16 08:38:26 +00:00
Bob Wilson
dbab14b8ea Record landing pads with a SmallSetVector to avoid multiple entries.
There may be many invokes that share one landing pad, and the previous code
would record the landing pad once for each invoke.  Besides the wasted
effort, a pair of volatile loads gets inserted every time the landing pad is
processed.  The rest of the code can get optimized away when a landing pad
is processed repeatedly, but the volatile loads remain, resulting in code like:

LBB35_18:
Ltmp483:
        ldr     r2, [r7, #-72]
        ldr     r2, [r7, #-68]
        ldr     r2, [r7, #-72]
        ldr     r2, [r7, #-68]
        ldr     r2, [r7, #-72]
        ldr     r2, [r7, #-68]
        ldr     r2, [r7, #-72]
        ldr     r2, [r7, #-68]
        ldr     r2, [r7, #-72]
        ldr     r2, [r7, #-68]
        ldr     r2, [r7, #-72]
        ldr     r2, [r7, #-68]
        ldr     r2, [r7, #-72]
        ldr     r2, [r7, #-68]
        ldr     r2, [r7, #-72]
        ldr     r2, [r7, #-68]
        ldr     r4, [r7, #-72]
        ldr     r2, [r7, #-68]

llvm-svn: 144787
2011-11-16 07:57:21 +00:00
Craig Topper
7a4d482aaa Fix the execution domain on a bunch of SSE/AVX instructions.
llvm-svn: 144784
2011-11-16 07:30:46 +00:00
Bob Wilson
45ab17a709 Update the SP in the SjLj jmpbuf whenever it changes. <rdar://problem/10444602>
This same basic code was in the older version of the SjLj exception handling,
but it was removed in the recent revisions to that code.  It needs to be there.

llvm-svn: 144782
2011-11-16 07:12:00 +00:00
Bob Wilson
0e88464871 Fix ARM SjLj-EH dispatch setup code. <rdar://problem/10444602>
The EmitBasePointerRecalculation function has 2 problems, one minor and one
fatal.  The minor problem is that it inserts the code at the setjmp
instead of in the dispatch block.  The fatal problem is that at the point
where this code runs, we don't know whether there will be a base pointer,
so the entire function is a no-op.  The base pointer recalculation needs to
be handled as it was before, by inserting a pseudo instruction that gets
expanded late.

Most of the support for the old approach is still here, but it no longer
has any connection to the eh_sjlj_dispatchsetup intrinsic.  Clean up the
parts related to the intrinsic and just generate the pseudo instruction
directly.

llvm-svn: 144781
2011-11-16 07:11:57 +00:00
Craig Topper
d842079270 Remove code to enable execution dependency fix pass on VR256. VR128 is sufficient after r144636.
llvm-svn: 144777
2011-11-16 05:02:04 +00:00
Evan Cheng
ab9e2ad9c4 Revert r144568 now that r144730 has fixed the fast-isel kill marker bug.
llvm-svn: 144776
2011-11-16 04:55:01 +00:00
Nick Lewycky
29efc8f15d Fix typo in test.
llvm-svn: 144774
2011-11-16 03:56:38 +00:00
Nick Lewycky
ff690249a9 Merge isObjectPointerWithTrustworthySize with getPointerSize. Use it when
looking at the size of the pointee. Fixes PR11390!

llvm-svn: 144773
2011-11-16 03:49:48 +00:00
Evan Cheng
65d5df1165 If the 2addr instruction has other kills, don't move it below any other uses since we don't want to extend other live ranges.
llvm-svn: 144772
2011-11-16 03:47:42 +00:00
Evan Cheng
27c17a65d1 RescheduleKillAboveMI() must backtrack to before the rescheduled DBG_VALUE instructions. rdar://10451185
llvm-svn: 144771
2011-11-16 03:33:08 +00:00
Evan Cheng
d756c3ec65 Process all uses first before defs to accurately capture register liveness. rdar://10449480
llvm-svn: 144770
2011-11-16 03:05:12 +00:00
Eli Friedman
c2a46f1a90 Fix testcase.
llvm-svn: 144769
2011-11-16 03:03:52 +00:00
Eli Friedman
1f3d774ba4 CONCAT_VECTORS can have more than two operands. PR11389.
llvm-svn: 144768
2011-11-16 02:52:39 +00:00
Eli Friedman
ce0cea66b9 Add a couple asserts so it will be easier to debug if we accidentally pass indexed loads/stores to the legalizer.
llvm-svn: 144767
2011-11-16 02:43:15 +00:00
Michael J. Spencer
d410d36be0 Remove extra ,.
llvm-svn: 144759
2011-11-16 01:36:50 +00:00
Kostya Serebryany
4105068ea9 AddressSanitizer, first commit (compiler module only)
llvm-svn: 144758
2011-11-16 01:35:23 +00:00